Patents Examined by Yaima Rigol
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Patent number: 11681471Abstract: The described technology is generally directed towards a streaming data storage system that can switch between a tiered mode of operation in which events are written to Tier-1 storage and later migrated to Tier-2 storage, and a direct mode of operation in which events are written to Tier-2 storage, bypassing the tiered mode. The switching from tiered mode to direct mode, and from direct mode to tiered mode, can be automatic and based on user configuration information. For example, an event size metric (e.g., average event size) can be evaluated against user defined thresholds to determine which mode to use. If the average event size goes below a low threshold value, the tiered mode is switched to and used for appending events to a segment of a data stream. If the average event size goes above a high threshold value, the direct mode is switched to and used.Type: GrantFiled: April 7, 2021Date of Patent: June 20, 2023Assignee: EMC IP HOLDING COMPANY LLCInventor: Andrei Paduroiu
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Patent number: 11681622Abstract: Described herein is a memory architecture that is configured to dynamically determine an address encoding to use to encode multi-dimensional data such as multi-coordinate data in a manner that provides a coordinate bias corresponding to a current memory access pattern. The address encoding may be dynamically generated in response to receiving a memory access request or may be selected from a set of preconfigured address encodings. The dynamically generated or selected address encoding may apply an interleaving technique to bit representations of coordinate values to obtain an encoded memory address. The interleaving technique may interleave a greater number of bits from the bit representation corresponding to the coordinate direction in which a coordinate bias is desired than from bit representations corresponding to other coordinate directions.Type: GrantFiled: December 14, 2021Date of Patent: June 20, 2023Assignee: Pony AI Inc.Inventors: Yubo Zhang, Pingfan Meng
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Patent number: 11675710Abstract: Systems, apparatuses, and methods for limiting translation lookaside buffer (TLB) searches using active page size are described. A TLB stores virtual-to-physical address translations for a plurality of different page sizes. When the TLB receives a command to invalidate a TLB entry corresponding to a specified virtual address, the TLB performs, for the plurality of different pages sizes, multiple different lookups of the indices corresponding to the specified virtual address. In order to reduce the number of lookups that are performed, the TLB relies on a page size presence vector and an age matrix to determine which page sizes to search for and in which order. The page size presence vector indicates which page sizes may be stored for the specified virtual address. The age matrix stores a preferred search order with the most probable page size first and the least probable page size last.Type: GrantFiled: September 9, 2020Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: John D. Pape, Brian R. Mestan, Peter G. Soderquist
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Patent number: 11675504Abstract: A memory controller includes a key generator, an encryption and decryption circuit, and a processor. The key generator generates a first security key and a second security key based on a write request from a host. The encryption and decryption circuit encrypts write data corresponding to the write request based on the first security key to generate encrypted write data, and encrypts the first security key based on the second security key to generate a first encrypted security key. The processor controls nonvolatile memories such that the encrypted write data, the first encrypted security key, and the second security key are programmed in at least one of the nonvolatile memories, and controls the nonvolatile memories such that a dummy program operation is performed on a page of the nonvolatile memories in which the second security key is programmed instead of erasing the encrypted write data.Type: GrantFiled: April 7, 2021Date of Patent: June 13, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Myeongjong Ju, Seungjae Lee, Jisoo Kim
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Patent number: 11663121Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.Type: GrantFiled: November 20, 2021Date of Patent: May 30, 2023Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Patent number: 11640358Abstract: A vehicular device includes multiple CPU modules, multiple cache memories allocated to the CPU modules, respectively, and a memory synchronization unit configured to synchronize multiple surfaces drawn in the multiple cache memories. The memory synchronization unit divides the surfaces to be synchronized into multiple tiles, and sequentially synchronize the divided tiles from tiles for which drawing has been completed.Type: GrantFiled: October 12, 2021Date of Patent: May 2, 2023Assignee: DENSO CORPORATIONInventor: Nobuhiko Tanibata
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Patent number: 11635894Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: GrantFiled: March 15, 2019Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Carminantonio Manganelli, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Patent number: 11635919Abstract: A computing device including executable processes may determine that a future likelihood of access for virtual memory pages of an executable process are below a threshold likelihood of access based on an execution status of the executable process or a tracking of memory accesses to the virtual memory pages of the executable process. Responsive to this determination, memory pages found to store contents matching that of memory pages mapped to other processes may be unmapped from the process and released for reuse by the computing device. The virtual memory pages may then be marked as being shared with the similar memory pages mapped to the other processes. At a later time, the memory pages of the process may be configured to be non-shared, the configuring including either copying respective shared pages to non-shared pages or enabling a processor exception on access to the memory pages.Type: GrantFiled: September 30, 2021Date of Patent: April 25, 2023Assignee: Amazon Technologies, Inc.Inventors: Martin Pohlack, Peter Barry, Filippo Sironi
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Patent number: 11609861Abstract: A method includes synthetizing a hardware description language (HDL) code into a netlist comprising a first a second and a third components. The method further includes allocating addresses to each component of the netlist. Each allocated address includes assigned addresses and unassigned addresses. An internal address space for a chip is formed based on the allocated addresses. The internal address space includes assigned addresses followed by unassigned addresses for the first component concatenated to the assigned addresses followed by unassigned addresses for the second component concatenated to the assigned addresses followed by unassigned addresses for the third component. An external address space for components outside of the chip is generated that includes only the assigned addresses of the first component concatenated to the assigned addresses of the second component concatenated to the assigned addresses of the third component. Internal addresses are translated to external addresses and vice versa.Type: GrantFiled: July 31, 2020Date of Patent: March 21, 2023Assignee: Marvell Asia Pte LtdInventors: Saurabh Shrivastava, Shrikant Sundaram, Guy T. Hutchison
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Patent number: 11609859Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.Type: GrantFiled: November 17, 2020Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Brian J. Slechta
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Patent number: 11599287Abstract: A method of managing blocks in a flash memory includes: detecting states of blocks of a reserved area in the flash memory and building a bad block management table accordingly; recording mappings between bad blocks of an user area in the flash memory and good blocks of the reserved area into the bad block management table; when the bad block management table indicates there is no good block remaining in the reserved area that can be mapped to, selecting one of bad blocks of the reserved area or the user area and obtaining a recollected block after erasing the selected bad block; recording a mapping between the recollected block and a bad block in the user area into the bad block management table; and based on the bad block management table, programming data into the recollected block.Type: GrantFiled: July 6, 2021Date of Patent: March 7, 2023Assignee: Realtek Semiconductor Corp.Inventors: Hua Zeng, Mingrui Li, Kui Rong
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Patent number: 11593030Abstract: The described technology is generally directed towards cross-stream transactions in a streaming data storage system, which allows a writer application to commit multiple events to distinct data streams in a single transaction. The system creates a cross-stream transaction for a writer application, and the writer application adds events to the cross-stream transaction, indicating which destination data stream(s) each event's data is to be appended. The system adds the event to a subordinate transaction created for each specified data stream. Upon committing the cross-stream transaction, the system coordinates the committing of the subordinate transactions to their respective data streams.Type: GrantFiled: May 11, 2021Date of Patent: February 28, 2023Assignee: EMC IP HOLDING COMPANY LLCInventors: Mikhail Danilov, Yohannes Altaye
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Patent number: 11580017Abstract: The invention relates to a method, a non-transitory computer program product, and an apparatus for managing data storage. The method performed by a flash controller includes: obtaining information indicating a subregion to be activated, where the subregion is associated with a logical block address (LBA) range; triggering a garbage collection (GC) process being performed in background to migrate user data of all the or a portion of the LBA range associated with the subregion to continuous physical addresses in a flash device; and updating content of a plurality of entries associated with the subregion according to migration results, where each entry includes information indicating which physical address that user data of a corresponding logical address is physically stored in the flash device.Type: GrantFiled: January 28, 2021Date of Patent: February 14, 2023Assignee: SILICON MOTION, INC.Inventor: Kuan-Yu Ke
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Patent number: 11573899Abstract: Low latency in a non-uniform cache access (“NUCA”) cache in a computing environment is provided. A first compressed cache line is interleaved with a second compressed cache line into a single cache line of the NUCA cache, where data of the first compressed cache line is stored in one or more even sectors in the single cache line and stored in zero or more odd sectors in the single cache line after the data fills the one or more even sectors, and data of the second compressed cache line is stored in the one or more odd sectors in the single cache line and stored in zero or more even sectors in the single cache line after the data fills the one or more odd sectors.Type: GrantFiled: October 21, 2021Date of Patent: February 7, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Deanna Postles Dunn Berger
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Patent number: 11573724Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.Type: GrantFiled: June 5, 2019Date of Patent: February 7, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Arkaprava Basu, Mitesh R. Meswani, Dibakar Gope, Sooraj Puthoor
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Patent number: 11573794Abstract: An application thread executes concurrently with a garbage collection (GC) thread traversing a call stack of the application thread. Frames of the call stack that have been processed by the GC thread assume a global state associated with the GC thread. The application thread may attempt to return to a target frame that has not yet assumed the global state. The application thread hits a frame barrier, preventing return to the target frame. The application thread determines a frame state of the target frame. The application thread selects appropriate operations for bringing the target frame to the global state based on the frame state. The selected operations are performed to bring the target frame to the global state. The application thread returns to the target frame.Type: GrantFiled: March 25, 2021Date of Patent: February 7, 2023Assignee: Oracle International CorporationInventors: Erik Österlund, Per Liden, Stefan Mats Rikard Karlsson
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Patent number: 11567700Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.Type: GrantFiled: April 6, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Patrick A. La Fratta, Robert Walker
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Patent number: 11567670Abstract: A Solid State Drive (SSD) is disclosed. The SSD may comprise flash storage for data, the flash storage organized into a plurality of blocks. A controller may manage reading data from and writing data to the flash storage. Metadata storage may store device-based log data for errors in the SSD. Identification firmware may identify a block responsive to the device-based log data. In some embodiments of the inventive concept, verification firmware may determine whether the suspect block is predicted to fail responsive to both precise block-based data and the device-based log data.Type: GrantFiled: December 2, 2019Date of Patent: January 31, 2023Inventors: Nima Elyasi, Changho Choi
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Patent number: 11561715Abstract: A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.Type: GrantFiled: November 17, 2020Date of Patent: January 24, 2023Assignee: Netlist, inc.Inventor: Hyun Lee
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Patent number: 11561726Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.Type: GrantFiled: August 27, 2019Date of Patent: January 24, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Tingjun Xie, Zhenming Zhou, Zhenlei Shen, Chih-Kuo Kao