Abstract: A bus bar includes a laminated body formed by directly laminating a flat plate-shaped first conductive plate, flat plate-shaped insulating sheet, and flat plate-shaped second conductive plate. The laminated body has main terminal connection parts into which end portions of external connection terminals are inserted, and is sealed in a sealing body, except the main terminal connection parts. The first conductive plate, insulating sheet, and second conductive plate are pressurized toward the insulating sheet in the lamination direction of the laminated body so that volumes of air spaces inside the insulating sheet (and air spaces between the first conductive plate and the insulating sheet and between the second conductive plate and the insulating sheet) are compressed.

Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

Abstract: Provided is a semiconductor device including: a laminated substrate in which a circuit layer, an insulating layer, and a metal layer are sequentially laminated. A slit is formed in the circuit layer. A recess recessed from one surface side facing the insulating layer toward the other surface side is formed in the metal layer. The recess of the metal layer has a relaxation portion at least partially overlapping the slit of the circuit layer in a planar view.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a first dielectric feature separating the gate structure into a first portion and a second portion. The semiconductor structure also includes a metal layer formed over the gate structure. In addition, top surfaces of the first portion and the second portion of the gate structure and a top surface of the first dielectric feature are covered by the metal layer.

Abstract: According to one embodiment, a magnetoresistance memory device includes: a first conductor; a variable resistance material on a top surface of the first conductor; a second conductor on a top surface of the variable resistance material; a first insulator other than nitride on a top surface of the second conductor; a magnetoresistance effect element on a top surface of the first insulator; and a third conductor located on a side surface of the first insulator and extending on a side surface of the second conductor and a side surface of the magnetoresistance effect element.

Abstract: An image sensor includes: on a substrate that includes a first surface and a second surface opposite to the first surface, photoelectric conversion regions located in the substrate, the photoelectric conversion regions being separated from each other; partition layers spaced apart from the first surface and between the photoelectric conversion regions; and pixel separation layers on the partition layers that separate the photoelectric conversion regions from each other.

Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes: a substrate and a magnetic tunnel junction on the substrate. The magnetic tunnel junction includes: a bottom electromagnetic structure on the substrate, an insulating layer on the bottom electromagnetic structure, and a top electromagnetic structure on the insulating layer. The semiconductor structure further includes a sidewall tunneling layer on sidewall surfaces of the magnetic tunnel junction.

Abstract: A semiconductor device structure includes a first conductive structure and a second conductive structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer disposed over the first conductive structure, and a second spacer disposed over the second conductive structure. The semiconductor device structure further includes a third spacer disposed over a sidewall of the first spacer, and a fourth spacer disposed over a sidewall of the second spacer. A lower portion of the third spacer adjoins a lower portion of the fourth spacer, and an air gap is covered by the lower portion of the third spacer and the lower portion of the fourth spacer.

Abstract: An image sensor includes a first chip including a pixel region, a pad region, and an optical black region interposed between the pixel region and the pad region, and a second chip being in contact with a first surface of the first chip and including circuits for driving the first chip. The first chip includes a first substrate, a device isolation portion disposed in the first substrate and defining unit pixels, an interlayer insulating layer interposed between the first substrate and the second chip, a connection wiring structure disposed in the interlayer insulating layer, and a connection contact plug disposed in the interlayer insulating layer and connecting the connection wiring structure to the device isolation portion in the optical black region. The image sensor further includes a conductive pad disposed in the first chip or the second chip.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first insulating member, and a nitride member. The third electrode includes a first electrode portion. The first electrode portion is between the first and second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The second semiconductor region includes first and second semiconductor portions. The first semiconductor portion is electrically connected with the first electrode. The second semiconductor portion is electrically connected with the second electrode. The first insulating member includes a first insulating region. The first insulating region is between the third partial region and the first electrode portion. The nitride member includes a first nitride region.

Abstract: A wafer dividing method includes forming modified layers which will be starting points of division, integrally attaching an annular frame and the wafer together through a dicing tape, directing the wafer downward and expanding the dicing tape to divide, into individual device chips, the wafer along the modified layers formed along the streets, counting particles scattered at the time of division of the wafer by a particle counter disposed in a dust collection path set directly below the wafer, and determining, on the basis of the number of the particles, whether or not the modified layers have been properly formed, at the time of carrying out the dividing step.

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

Abstract: This disclosure relates to the displaying technical field, and provides an array substrate and a display device. The array substrate includes a base substrate, data lines and pixel electrodes. The data lines include adjacent first and second data lines. The pixel electrodes include at least one bridge pixel electrode, an orthographic projection of which on the base substrate is between orthographic projections of the first data line and the second data line on the base substrate. A first notch is provided on a side of the bridge pixel electrode close to the first data line, and a second notch is provided on a side of the bridge pixel electrode close to the second data line. The bridge pixel electrode of the array substrate has a similar lateral field capacitance to the data lines on both sides, thus reducing voltage crosstalk of the bridge pixel electrode and improving the display effect.

Abstract: Embodiments of the present disclosure provide a display substrate and a display apparatus. The display substrate comprises: multiple repetition units, where at least one repetition unit includes multiple subpixels including first subpixels and second subpixels. In the first subpixel, an orthographic projection of an anode adapter portion on a base substrate does not overlap an orthographic projection of a drive active layer on the base substrate, and an orthographic projection of a main body portion on the base substrate does not overlap the orthographic projection of the anode adapter portion on the base substrate. In the second subpixel, an orthographic projection of an anode adapter portion on the base substrate overlaps an orthographic projection of a drive active layer on the base substrate, and an orthographic projection of a main body portion on the base substrate overlaps the orthographic projection of the anode adapter portion on the base substrate.

Abstract: Provided is a non-volatile memory package that is electrically optimized with a plurality of different non-volatile memory chips through a ball map, by fixing positions of buffer chips connected to the plurality of different non-volatile memory chips.

Abstract: A preceding wafer is transported from a chamber of a heat treatment apparatus after processing on the preceding wafer is completed. A temperature within the chamber at a time when the preceding wafer is transported from the chamber is defined as a transportation temperature, and a difference between a measurement temperature within the chamber measured after the preceding wafer is transported from the chamber and the transportation temperature is calculated as a decreasing temperature. The calculated decreasing temperature and a predetermined threshold value are compared with each other. When the decreasing temperature is larger than the threshold value, dummy processing of preheating an in-chamber structure such as a susceptor by light irradiation from halogen lamps and flash lamps is executed. In contrast, when the decreasing temperature is equal to or smaller than the threshold value, the dummy processing is not executed but processing on a subsequent substrate is started.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.

Abstract: A technique advantageous for improving an optical property of a photoelectric conversion apparatus is provided. The photoelectric conversion apparatus includes a photoelectric conversion layer and a light-shielding film that covers the photoelectric conversion layer, wherein the light-shielding film includes one metallic layer and another metallic layer located between the one metallic layer and the photoelectric conversion layer.

Abstract: Method of doping a semiconductor sample in a uniform and carbon-free way, wherein said sample has a surface, comprising the following steps: A. removing oxides from at least part of the said surface; B. dip coating said at least part of the surface of the sample in a dopant based carbon-free solution of at least one dopant based carbon free substance diluted in water, wherein said at least one dopant based carbon free substance has a molecule comprising at least one dopant atom, wherein the dip coating is achieved by heating said dopant based carbon-free solution at a dip coating temperature from 65% to 100% of the boiling temperature of said dopant based carbon-free solution, thereby a self-assembled mono-layer including dopant atoms is formed; C. annealing said sample, wherein the annealing is configured to cause said dopant atoms included in said self-assembled mono-layer to be diffused into the sample.

Abstract: A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.