Patents Examined by Yasser Abdelaziez
  • Patent number: 10737933
    Abstract: Flush mount sensor packages and packaging methods for micromachined transducers, which can be used for fluid flow measurements, are provided. A sensor package can include a substrate, a sensor mounted on a front side of the substrate, a wire bond coupled to the sensor and passing through the substrate, and a shim cap positioned around the sensor. The wire bond does not protrude above the topside of the sensor, and the shim cap and the sensor can be substantially flush.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: August 11, 2020
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Tiffany N. Reagan, Mark Sheplak, Dylan P. Alexander
  • Patent number: 10741385
    Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 11, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Gido Van Der Star, Toshiya Suzuki
  • Patent number: 10741714
    Abstract: An infrared detection device includes a semiconductor substrate; a first metamorphic buffer layer that is formed on the semiconductor substrate; a first contact layer that is formed on the first metamorphic buffer layer; a first infrared absorption layer that is formed on the first contact layer; a second contact layer that is formed on the first infrared absorption layer; a second metamorphic buffer layer that is formed on the second contact layer; a third contact layer that is formed on the second metamorphic buffer layer; a second infrared absorption layer that is formed on the third contact layer; a fourth contact layer that is formed on the second infrared absorption layer; a lower electrode that is connected with the first contact layer; an upper electrode that is connected with the fourth contact layer; and an intermediate electrode that is connected with the second contact layer and the third contact layer.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 11, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Patent number: 10734301
    Abstract: The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 4, 2020
    Assignee: Qorvo US, Inc.
    Inventor: Robert Charles Dry
  • Patent number: 10734294
    Abstract: An SEM image is acquired. The SEM image shows a metal line and a via hole disposed above the metal line. The via hole exposes a portion of the metal line vertically aligned with the via hole. A first portion and a second portion of the via hole are each vertically not aligned with the metal line and are disposed on opposite sides of the metal line. The acquired SEM image is processed to enhance a contrast between the first and second portions and their surrounding areas. A first dimension of the first portion and a second dimension of the second portion of the via hole are measured in a first direction. The first direction is different from a second direction along which the metal line extends. An overlay between the via hole and the metal line is determined based on the first dimension and the second dimension.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming Ho, Po Shun Lin, Venkata Sripathi Sasanka Pratapa, Yi-Ju Wang
  • Patent number: 10734272
    Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh
  • Patent number: 10727378
    Abstract: An optical wavelength conversion member and a light-emitting device including the optical wavelength conversion member. The optical wavelength conversion member (9) is formed of a ceramic sintered body having a fluorescent phase containing fluorescent crystal grains as a main component and a translucent phase containing translucent crystal grains as a main component. Crystal grains of the fluorescent phase have a composition represented by formula A3B5O12:Ce, where the element A is selected from Sc, Y, and lanthanoids (except for Ce), and the element B is selected from Al and Ga. In the optical wavelength conversion member (9), 0.3<a<34 and 300 ?m<y<1,050 ?m are satisfied, wherein a represents the area ratio of the translucent phase to the fluorescent phase in a cross section of the optical wavelength conversion member (9), and y represents the interfacial length of the fluorescent phase.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: July 28, 2020
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Shohei Takaku, Yusuke Katsu, Tsuneyuki Ito, Yuki Shimura, Takeshi Mitsuoka, Jun Moteki
  • Patent number: 10726966
    Abstract: Disclosed is a method of forming a conductive polymer thin film pattern, including (a) Coating substrate with solution including PEDOT:PSS (poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate)) to form coating layer including solution on substrate, (b) irradiating a predetermined portion of the coating layer with light, thus manufacturing a pre-patterned substrate including PEDOT:PSS patterned on the predetermined portion and the coating layer other than the predetermined portion, and (c) removing the coating layer from the pre-patterned substrate, thus manufacturing a conductive polymer thin film having a PEDOT:PSS pattern.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 28, 2020
    Assignee: Korea Institute of Industrial Technology
    Inventors: Changhun Yun, Hyeck Go
  • Patent number: 10727232
    Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Arvind Kumar, Mahendra Pakala, Sanjeev Manhas, Satendra Kumar Gautam
  • Patent number: 10720569
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Johnathan D. Harms
  • Patent number: 10711193
    Abstract: A quantum dot, a method of producing the same, a quantum dot polymer composite including the same, and an electronic device. The quantum dot includes a core including a first semiconductor nanocrystal and a shell disposed on the core, the shell including a second semiconductor nanocrystal and a metal dopant, wherein the first semiconductor nanocrystal includes a Group II-VI compound, a Group III-V compound, or a combination thereof, the second semiconductor nanocrystal includes a Group II-VI compound, and the metal dopant includes hafnium, zirconium, titanium, or a combination thereof.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongwook Kim, Sungwoo Hwang, Soo Kyung Kwon, Yuho Won, Eun Joo Jang, Hyo Sook Jang
  • Patent number: 10714602
    Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
  • Patent number: 10713556
    Abstract: Processing raw data stored in an historian device for determining an amount of products passed through a process element in a process control environment is described. A count value is incremented by a counter at a rate at which products pass through the process element. The count value rolls over to zero when the count value reaches a rollover value R. An historian device periodically receives count value data points from the counter. A deadband value D is set in the historian device for distinguishing between rollovers, resets, and reversals. A client device queries the historian device for an amount of products passed through the process element for a timeframe. The historian device selects a set of count value data points from within the queried timeframe. The historian device determines, based on the selected data points and their quality, an amount of products passed through the process element.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: July 14, 2020
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Vinay T. Kamath, Yevgeny Naryzhny, Alexander Vasilyevich Bolotskikh, Abhijit Manushree, Elliott Middleton, Bala Kamesh Sista
  • Patent number: 10714550
    Abstract: An organic light-emitting display apparatus prevents the quality of an image being displayed thereon from being deteriorated as a result of contamination of an organic emission layer. The display apparatus includes a substrate with a display area and a periphery area. A first insulating layer, disposed over the substrate, has a first opening in the periphery area. A first electrode is disposed within the display area, over the first insulating layer. A first bank is disposed over the first insulating layer and has a second opening through which a center of the first electrode is exposed. A second bank is disposed over the first insulating layer and is separated from the first bank. The first opening is disposed between the first bank and the second bank. An intermediate layer is disposed over the first electrode. A second electrode is disposed over the intermediate layer and the first bank.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Deukjong Kim, Donghyun Lee, Sangki Kim
  • Patent number: 10707141
    Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Osamu Usui, Yuji Imoto
  • Patent number: 10705495
    Abstract: A load control system may include control devices for controlling power provided to an electrical load. The control devices may include a control-source device and a control-target device. The control-target device may control the power provided to the electrical load based on digital messages received from the control-source device. The control devices may include a load control discovery device capable of sending discovery messages configured to discover control devices within a location. The discovered control devices may be organized by signal strength and may be provided to a network device to enable association of the discovered control devices within a location. The discovery messages may be transmitted within an established discovery range. The discovery range may be adjusted to discover different control devices. Different control devices may be identified as the load control discovery device for discovering different control devices.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 7, 2020
    Assignee: Lutron Technology Company LLC
    Inventors: Kyle Thomas Barco, Bryan Robert Barnes, Erica L. Clymer, Brian Michael Courtney, Jordan H. Crafts, William Bryce Fricke, Galen Edgar Knode, Sanjeev Kumar, Jonathan T. Lenz, Stephen M. Ludwig, Jr., Sandeep Mudabail Raghuram, Richard M. Walsh, III
  • Patent number: 10707340
    Abstract: In a general aspect, a silicon carbide (SiC) rectifier can include a substrate of a first conductivity type, a drift region of the first conductivity type, a junction field effect transistor (JFET) region of the first conductivity type, a body region of a second conductivity type, an anode implant region of the first conductivity type, and a channel of the first conductivity type. The channel can be in contact with and disposed between the JFET region and the anode implant region. A portion of the channel between the anode implant region and the JFET region can be disposed in the body region, The channel can be configured to be off under zero-bias conditions, and on at a positive turn-on voltage.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 7, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Andrei Konstantinov
  • Patent number: 10707341
    Abstract: A semiconductor device includes: a plurality of semiconductor switching elements that are a plurality of MOSFETs each including a Schottky barrier diode; a first ohmic electrode disposed above a first region of a well region and electrically connected to the first region, the first region being on the opposite side from a predefined region; a first Schottky electrode disposed on a semiconductor layer exposed at the first region of the well region; and a line electrically connected to the first ohmic electrode, the first Schottky electrode, and a source electrode. The device enables reduction of a breakdown in a gate insulating film.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 7, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukiyasu Nakao, Kohei Ebihara, Shiro Hino
  • Patent number: 10698427
    Abstract: Embodiments of the present disclosure include a method including receiving first impact data. The method includes receiving second impact data. The method includes applying a first filter to both the first impact data and the second impact data. The method includes applying a second filter to both the first impact data and the second impact data. Filtering includes time and frequency based discriminating filter to isolate specific signatures that representatively indicate impact signatures generated by the sand on the interrogator. The method includes comparing the first impact data and the second impact data for corresponding signatures. The method includes identifying a corresponding signature in both the first impact data and the second impact data. The method includes determining the corresponding signature meets a threshold criterion. The method includes determining one or more particulate properties based at least in part on the corresponding peak.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 30, 2020
    Assignee: GE OIL & GAS PRESSURE CONTROL LP
    Inventors: Vimal V. Shah, Lily Jiang, Lembit Salasoo
  • Patent number: 10699978
    Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer