Abstract: An array substrate, a preparing method thereof, a display panel and a display apparatus are disclosed. The array substrate includes: a base substrate (1); a driving circuit structure (2) on the base substrate (1); a planarization layer (3) and a plurality of electrode structures (4) successively located on a side, facing away from the base substrate (1), of the driving circuit structure (2); insulation structures (5) in gap areas between adjacent electrode structures (4); and pixel defining structures (6) on a side, facing away from the base substrate (1), of the insulation structures (5). The thickness of the insulation structures (5) is not smaller than the thickness of the electrode structures (4). An orthographic projection of the pixel defining structures (6) on the base substrate (1) at least completely covers the insulation structures (5).

Abstract: A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

Abstract: A micro-device structure comprises a source substrate having a sacrificial layer comprising a sacrificial portion adjacent to an anchor portion, a micro-device disposed completely over the sacrificial portion, the micro-device having a top side opposite the sacrificial portion and a bottom side adjacent to the sacrificial portion and comprising an etch hole that extends through the micro-device from the top side to the bottom side, and a tether that physically connects the micro-device to the anchor portion. A micro-device structure comprises a micro-device disposed on a target substrate. Micro-devices can be any one or more of an antenna, a micro-heater, a power device, a MEMs device, and a micro-fluidic reservoir.

Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method can comprise forming a MEMS layer based on fusion bonding a handle MEMS with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.

Abstract: A micromechanical sensor device and manufacturing method. The micromechanical sensor device is provided with a cap substrate, which has a first front side and a first back side, and which has a through-opening as a media entry region; and with a sensor substrate, which has a second front side and a second back side, and which has, on the second front side, a sensor region that is embedded in an island-like region suspended on the remaining sensor substrate. The island-like region is mechanically decoupled from the remaining sensor substrate by a lateral stress-relief trench and by a cavity situated in the sensor substrate, underneath the island-like region. The first back side is bonded to the second front side so that the through opening is situated above the sensor region. The sensor region is covered by a gel, which fills the through-opening and the stress-relief trench at least partially.

Abstract: A hollow package (103) includes a substrate (109), an element (111), a partition wall (113), and a top plate (115) and has one or more closed hollow parts (117) that are covered by the substrate (109), the partition wall (113), and the top plate (115), and the substrate (109), the partition wall (113), and the top plate (115) are sealed with a cured product of a sealing resin composition. The top plate (115) and the partition wall (113) are composed of an organic material, and the thickness of the top plate (115), the thickness of the partition wall (113), the width of the partition wall, and the maximum width of the hollow part (117) are each within respective predetermined ranges. The sealing resin composition comprises (A) an epoxy resin that includes one or more selected from the group consisting of an epoxy resin containing two epoxy groups in the molecule and an epoxy resin containing three or more epoxy resins in the molecule and (B) an inorganic filler.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.

Abstract: A display device includes first power supply terminal electrodes and second power supply terminal electrodes. The first power supply terminal electrodes in a first terminal portion of a frame area at least partially overlap, in a plan view, at least a part of the second power supply terminal electrodes in a second terminal portion of a flexible printed board. The second power supply terminal electrodes are electrically connected to the first power supply terminal electrodes. Either the first power supply terminal electrodes or the second power supply terminal electrodes are inclined from the others.

Abstract: One example includes a superconducting circuit. The circuit superconducting circuitry fabricated on a first surface of a circuit layer. The circuit layer includes a dielectric material. The circuit also includes a metal layer formed on a second surface of the circuit layer opposite the first surface and a through-substrate via (TSV) conductively coupled to the metal layer and extending through the circuit layer to the first surface. The circuit further includes a flux gasket conductively coupled to and extending from the TSV on the first surface proximal to the superconducting circuitry. The flux gasket can be configured to divert magnetic fields away from the superconducting circuitry.

Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a first transistor. The first transistor includes a first semiconductor layer, and the first semiconductor layer includes bismuth selenium oxide materials to enhance mobility of the first transistor and improve electrical performance of the display panel, so that the display panel meets requirements of high refresh rate and high transmittance.

Abstract: Provided are a method for preparing an organic electroluminescent device, an organic electroluminescent device and a display apparatus.

Abstract: An active matrix LED array precursor forming a precursor to a micro LED array is provided. The active matrix LED array precursor comprises a common first semiconducting layer comprising a substantially undoped Group III-nitride, a plurality of transistor-driven LED precursors, and a common source contact. Each transistor-driven LED precursor comprises a monolithic light emitting diode (LED) structure comprising a plurality of III-nitride semiconducting layers, a barrier semiconducting layer, and a gate contact. Each monolithic LED structure is formed on a portion of the common semiconducting layer. The barrier semiconducting is layer formed on a portion of the common semiconducting layer encircling the LED structure and configured to induce a two-dimensional electron channel layer at the interface between the common semiconducting layer and the barrier semiconducting layer. The gate contact is formed over a portion of the two-dimensional electron channel layer, the gate contact encircling the LED structure.

Abstract: A semiconductor substrate includes a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, and a second semiconductor layer coupled to the first dielectric layer. The second semiconductor layer includes a base portion substantially aligned with the first dielectric layer and a cantilever portion protruding from an end of the first dielectric layer. The cantilever portion includes a tapered surface tapering from a bottom surface of the second semiconductor layer toward a top surface of the second semiconductor layer.

Abstract: A production line device prepares a superconducting circuit layer on a substrate. The device prepares an under bump metallization (UBM) layer on an upper surface of the superconducting circuit layer. A superconducting connection is formed between the UBM layer and the superconducting circuit layer. The production device prepares a welding spot on an upper surface of the UBM layer to obtain a qubit assembly configured for a flip-chip superconducting quantum chip. A superconducting electrical connection is formed between the welding spot and the UBM layer.

Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electronic device, and the like are provided.

Abstract: An array substrate is disclosed and includes: a base substrate (1); an excitation light source (2) on a side of the base substrate (1); and a sub pixel on a side of the excitation light source (2) facing away from the base substrate (1). The sub pixel at least includes a first-kind sub pixel (3). The first-kind sub pixel (3) includes a first quantum dot conversion layer (31), a first recycling component layer (32) and a first color film layer (33) sequentially located on the side of the excitation light source (2) facing away from the base substrate (1), and the first recycling component layer (32) is configured to limit at least part of light with a wavelength smaller than a wavelength of emergent light of the first-kind sub pixel (3) into the first recycling component layer (32) and the first quantum dot conversion layer (31).

Abstract: The present disclosure relates to magnetic devices. In particular, the disclosure relates to magnetic memory and logic devices that employ the voltage control of magnetic anisotropy (VCMA) effect for magnetization switching. The present disclosure provides a method for manufacturing a magnetic structure for such a magnetic device. The method comprising the following steps: providing a bottom electrode layer, forming a SrTiO3 (STO) stack on the bottom electrode layer by atomic layer deposition (ALD) of at least two different STO nanolaminates, forming a magnetic layer on the STO stack, and forming a perpendicular magnetic anisotropy (PMA) promoting layer on the magnetic layer, the PMA promoting layer being configured to promote PMA in the magnetic layer.

Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

Abstract: Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.