Patents Examined by Yennhu B Huynh
  • Patent number: 7129129
    Abstract: A method of forming a trench in a semiconductor substrate includes a step of converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the litho for the active area, in particular a DRAM cell with a vertical transistor.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, David C. Ahlgren, Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 7119956
    Abstract: A liquid crystal display for use in applications where direct exposure to sunlight creates a thermal gradient from the front of the display to the back of the display uses a high efficiency iodine-type input polarizer and a high temperature type output polarizer. The output polarizer has a higher temperature rating than the input polarizer, so that the thermal gradient does not degrade display performance.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: October 10, 2006
    Assignee: Rockwell Collins, Inc.
    Inventor: James G. Sliney, Jr.
  • Patent number: 7102182
    Abstract: An example semiconductor device is capable of preventing a buried diffusion region formed near the bottom surface of a source trench from diffusing to the extent that it contacts a gate trench in the vicinity of that buried diffusion region even if the accuracy of the photographic step of trench formation is not so high. A side wall is formed on the circumferential side of the source trench and then impurities are injected to the bottom surface of the source trench. When the impurities are heated and diffused, the buried P+-type diffusion region is formed with a width almost identical to the width of the opening of the source trench or smaller than the width of the opening of the source trench. Thus, even when irregularities are generated in the manufacturing step and the buried diffusion region becomes larger than is necessary, it is possible to prevent contact of the buried diffusion region with the gate trench.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 5, 2006
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toshiyuki Takemori, Masato Itoi, Yuji Watanabe
  • Patent number: 7079201
    Abstract: A fluorescent lamp for a backlight of a liquid crystal display device and a liquid crystal display device having the same are disclosed. The fluorescent lamp includes a red color phosphor having a maximum luminous wavelength of about 600 nm to 620 nm, a green color phosphor having a maximum luminous wavelength of about 520 nm to 555 nm and a blue color phosphor having a maximum luminous wavelength of about 440 nm to 460 nm. The green color phosphor has one maximum luminous peak or the side peak having about 20% or smaller relative size in comparison with the maximum luminous peak beside the maximum luminous peak. Therefore, by removing or minimizing the side luminous peak of the green color phosphor, the color reproductivity can greatly increase without decreasing the brightness of the white color.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: July 18, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bo Sung Kim
  • Patent number: 7071007
    Abstract: A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: July 4, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chieh Tseng, Chao-Hsiung Wang, Tai-Bor Wu
  • Patent number: 7064001
    Abstract: A method of production of a semiconductor module comprised of a semiconductor chip, external connection terminal pads for bonding with solder balls or other external connection terminals, wires electrically connecting the same, and a sealing resin layer sealing the semiconductor chip, external connection terminal pds, and wires, where surfaces of the external connection terminal pads are exposed at bottoms of recesses formed in the sealing resin layer, comprising sealing by a resin external connection terminal pads and soluble metal layers formed at surfaces of the metal substrate by electroplating to form a sealing resin layer at that one surface, then etching away the metal substrate and soluble metal layers to thereby form in the resin sealing layer recesses exposing the external connection terminal pads at their bottoms by a single etching process without requiring special etching stop control.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: June 20, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Youichi Kazama, Keiichi Masaki
  • Patent number: 7064002
    Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: June 20, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ford B. Grigg
  • Patent number: 7056839
    Abstract: The invention provides an insulator having a main component of silicon dioxide, wherein the insulator includes at least one kind of organic polymer such as benzene nucleuses distributed therein in order to reduce a dielectric constant thereof as well as a method of forming the same.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: June 6, 2006
    Assignee: NEC Corporation
    Inventor: Kazuhiko Endo
  • Patent number: 7011978
    Abstract: The invention includes a capacitor construction. A capacitor electrode has a perovskite-type dielectric material thereover. The perovskite-type dielectric material has an edge region proximate the electrode, and a portion further from the electrode than the edge region. The portion has a different amount of crystallinity than the edge region. The invention also includes a method of forming a capacitor construction. A capacitor electrode is provided, and a perovskite-type dielectric material is chemical vapor deposited over the first capacitor electrode. The depositing includes flowing at least one metal organic precursor into a reaction chamber and forming a component of the perovskite-type dielectric material from the precursor. The precursor is exposed to different oxidizing conditions during formation of the perovskite-type dielectric material so that a first region of the dielectric material has more amorphous character than a second region of the dielectric material.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: March 14, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Cem Basceri
  • Patent number: 7008839
    Abstract: A substrate with a second semiconductor layer and a second mask film formed thereon is subjected to a heat treatment in an oxidizing atmosphere. Thus, second oxidized regions are formed through oxidization of the second semiconductor layer in regions of the second semiconductor layer that are not covered by the second mask film. At the same time, a second base layer is formed in each region that is interposed by the second oxidized regions. Then, the second mask film is removed, and a third semiconductor layer is selectively grown on the surface of the second base layer that is exposed between the second oxidized regions so as to cover the second oxidized regions, after which the first oxidized regions and the second oxidized regions covering the entire upper surface of the substrate are removed.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: March 7, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuzo Ueda, Hisashi Nakayama, Masaaki Yuri
  • Patent number: 7001813
    Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: February 21, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Michael James Manfra, Nils Guenter Weimann
  • Patent number: 6995075
    Abstract: Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer contains hydrogen mostly in form of hydrogen platelets oriented in parallel to each other and to neighboring crystal surface. The fragile layer is preferably grown within a single crystalline silicon wafer to facilitate the detachment of an overlaying thin layer of single crystalline silicon from the initial wafer. The hydrogen layer is grown on a seed layer. The seed layer is preferably formed by ion implantation of inert gases at doses in 1015 cm?2 range. The hydrogen layer is grown by plasma hydrogenation of the substrate. The hydrogenation process begins at substrate temperature not exceeding 250° C., and than continues at higher temperature not exceeding 400° C.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: February 7, 2006
    Assignee: Silicon Wafer Technologies
    Inventor: Alexander Usenko
  • Patent number: 6989302
    Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the n-type substrate (125). Other embodiments advantageously incorporate the method into methods for making PMOS devices.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: January 24, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Tim J. Makovicka, Alan L. Kordick
  • Patent number: 6987054
    Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: January 17, 2006
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
  • Patent number: 6987042
    Abstract: A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Naim Moumen, Porshia S. Wrschka
  • Patent number: 6987283
    Abstract: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: January 17, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani
  • Patent number: 6979609
    Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: December 27, 2005
    Assignee: Intel Corporation
    Inventors: Ian R. Post, Kaizad Mistry
  • Patent number: 6979657
    Abstract: The present invention provides a method for forming an improved dielectric layer for semiconductor devices such as gate structures and capacitors. The method utilizes a layer of (TaO)1?x(TiO)xN (x defined herein) as a substitute for SiO2, together with one or more additional procedures to minimize or prevent channel leakage and other problems that can minimize the performance of the structure.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: December 27, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwang-Chul Joo, Jae-Ok Kim
  • Patent number: 6977229
    Abstract: The present invention is provided to prevent yield reduction of semiconductor device in dry cleaning of semiconductor device manufacturing process. The electric action and chemical action due to plasma of a first gas generated by means of a plasma generating means and the physical action due to viscous friction force of high speed gas flow generated by means of a planar pad that is brought close to the main surface of a wafer are applied together for cleaning the main surface of the wafer. After cleaning, the wafer is exposed to plasma of a second gas in the same vacuum chamber and then transferred to the atmosphere.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: December 20, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Masaru Izawa
  • Patent number: 6977442
    Abstract: A semiconductor device includes a conductive layer with a plurality of wires, and a bonding pad formed in a region overlapping with the plurality of wires of the conductive layer. One of the wires is connected to the bonding pad, and an insulating protective film is formed between the remaining wires and the bonding pad. The protective film is bridged between adjacent wires at least in a region overlapping with the bonding pad. As a result, the protective film on the wires forms a bridge structure, which is effective in preventing cracking at a lower portion of the protective film. Further, a void formed underneath the bridged portion serves as an air spring to prevent damage to the structural elements, such as the wires, formed under the protective film. Further, because a polyimide film, which serves as a shock absorber, is not required, working efficiency can be improved and chip cost can be reduced.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 20, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masafumi Akagawa, Masahiro Horio