Abstract: The present invention is provided to prevent yield reduction of semiconductor device in dry cleaning of semiconductor device manufacturing process. The electric action and chemical action due to plasma of a first gas generated by means of a plasma generating means and the physical action due to viscous friction force of high speed gas flow generated by means of a planar pad that is brought close to the main surface of a wafer are applied together for cleaning the main surface of the wafer. After cleaning, the wafer is exposed to plasma of a second gas in the same vacuum chamber and then transferred to the atmosphere.

Abstract: The present invention describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips, many of said levels having a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level.

Abstract: A reflective liquid crystal display device having high reliability and excellent display is provided by preventing degradation and peeling of an organic film provided in order to impart an uneven shape to a reflective metal film. The reflective liquid crystal display has a configuration in which a liquid crystal layer is held in the space formed by a pair of substrates arranged opposing to each other and a seal member provided on the periphery portion of the substrate pair, an organic film, a reflective metal film, color filters, an overcoat film, an electrode substrate film, electrode layers, and an orientation film are laminated in order on the liquid crystal layer side of one substrate of the substrate pair, and the organic film is formed in the neighborhood region of the end of the seal member provided on the periphery portion of the aforementioned substrate.

Abstract: In a step of covering a rear face resist, by recognizing position of a positioning mark exposed at a rear face of a conductive foil, position recognition of a conductive pattern of the rear face of every block or every conductive foil is performed indirectly, and a resist layer is formed except an opening portion forming the scheduled rear face electrode on the conductive pattern. Therefore, a method of manufacturing a circuit device shortened in time.

Abstract: Disclosure is a method for a chemical mechanical polishing process for fabricating a semiconductor device. The method for performing the chemical mechanical polishing process for a copper layer on a semiconductor wafer comprises the steps of: performing the chemical mechanical polishing process for the copper layer on the semiconductor wafer by using slurry; performing a standstill process in a middle of the chemical mechanical polishing process; and carrying out the chemical mechanical polishing process again after performing the standstill process.

Abstract: A method of fabricating a stabilized TiN control wafer comprising the following steps. A silicon substrate is provided having a silicon oxide layer formed thereover. An initial TiN layer is formed over the silicon oxide layer. The silicon substrate is placed in an atmosphere having ambient oxygen for from about 22 to 26 hours to form a rested TiN layer. The rested TiN layer is heated at a temperature of from about 115 to 125° C. for from about 85 to 95 seconds to form a heat treated TiN layer, whereby the heat treated TiN layer is stabilized to form the stabilized TiN control wafer.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Abstract: A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.

Abstract: The present invention provides a method for manufacturing a semiconductor device capable of acquiring productivity when a p-type source/drain is formed by the implantation of a BF2 and B ions. The method for manufacturing a semiconductor device includes the steps of: implanting a BF2 ion in a p-type source/drain region on a silicon substrate with an ion implantation energy of from about 10 keV to about 20 keV; implanting B ion in the p-type source/drain region with an ion implantation energy of from about 5 keV to about 10 keV; and forming a p-type source/drain by carrying out a thermal treatment.

Abstract: The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt.

Abstract: Disclosed is a method for manufacturing a NAND flash device. After a source line plug hole is formed, a drain contact plug hole is formed. The holes are filled with a conductive material film and are then polished. It is therefore possible to simplify the process since a blanket etch process step is omitted. Moreover, loss of a drain contact plug by the blanket etch process is prevented. It is therefore possible to improve the electrical properties of a device and reduce the manufacturing cost price.

Abstract: A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the wafer. The probe fixture is retained at a test station either in a upright or an inverted position for testing and optical failure analysis. The probe fixture includes a position adjustment mechanism to locate the entire probe above the wafer and to more precisely position a tip of the probe on the IC. Optical failure analysis techniques are performed on the front side or the back side of the wafer while the wafer is retained in the test fixture and the probes are connected to the IC.

Abstract: A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100° C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

Abstract: A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.

Abstract: A probe of a scanning probe microscope (SPM) having a field-effect transistor (FET) structure at the tip of the probe, and a method of fabricating the probe are provided. The SPM probe having a source, channel, and drain is formed by etching a single crystalline silicon substrate into a V-shaped groove and doping the etching sloping sides at one end of the V-shaped groove with impurities.

Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.

Abstract: The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

Abstract: An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a layer over a substrate, and doping the layer with a dopant, after which the layer is laser thermal annealed. The layer can be a nitride, an oxide, or a polysilicon layer. The dopants can be arsenic, phosphorous, boron, or nitrogen. During the laser thermal annealing, certain portions of a surface of the semiconductor device are laser thermal annealed and other portions of a surface of the semiconductor device are not exposed. Also, the surface of the layer is smoother after the laser thermal annealing.

Abstract: The present invention relates to compounds of formula I ##STR1## or a salt, ester or amide thereof; wherein R.sup.1 is --CH.sub.2 --CH.sub.2 --, CH.sub.2 --O-- or --O--CH.sub.2 --; R.sup.2 and R.sup.3 are the same or different and are each hydrogen, C.sub.1-4 alkyl or taken together with the nitrogen comprise a nitrogen-containing heterocyclic ring having four to six ring members; R.sup.4 is a single bond or a C.sub.1-7 bivalent aliphatic hydrocarbon group and may be joined to the aromatic ring system at the 2,3,8 or 9 positions; n is 0 to 3, and their use as antihistamine and antiasthma agents.