Abstract: A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.

Abstract: An apparatus includes a radio frequency (RF) receiver to receive packets. The RF receiver includes first and second synchronization field detectors (SFDs). The first and second SFDs detect synchronization headers generated using first and second physical layer (PHY) modes, respectively.

Abstract: A radio frequency (RF) switch system, an RF switch protective circuit, and a protecting method thereof are provided. The RF switch system may include an RF switch and a protective circuit. The RF switch may be connected between a port that receives an RF signal and a ground. The protective circuit may detect a first voltage that is a voltage that is generated when the first RF switch is turned off, and may transmit an impedance value that is varied based on the first voltage to the port.

Abstract: Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.

Abstract: Aspects presented herein may enable a UE to determine whether phase continuity is to be maintained for one or more uplink transmissions when the UE is configured with a frequency-hopping with zero frequency offset. In one aspect, a UE receives, from a network entity, an indication of frequency hopping with zero frequency offset. The UE determines whether phase continuity is to be applied to UL transmissions based on the indication of the frequency hopping with zero frequency offset. The UE transmits, to the network entity, at least one uplink channel with no phase continuity based on the determination to not apply phase continuity to the UL transmissions.

Abstract: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

Abstract: The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.

Abstract: The present disclosure relates to a parallel filter structure for processing a signal. The parallel filter structure includes a signal input configured to receive a time and value discrete input signal. The parallel filter structure includes a feed forward equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The parallel filter structure includes a decision feedback equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit. Further, an oscilloscope and a method of processing a signal are provided.

Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

Abstract: A transmission apparatus that (i) generates a Quadrature Phase Shift Keying (QPSK) modulation signal s1(t) by applying a QPSK modulation scheme to a first data sequence, (ii) generates a 16-Quadrature Amplitude Modulation (QAM) modulation signal s2(t) by applying a 16-QAM modulation scheme to a second data sequence, (iii) generates a transmission signal z1(t) and a second transmission signal z2(t) by applying a phase hopping process, a precoding process, and a power adjust process to the QPSK modulation signal s1(t) and the 16-QAM modulation signal s2(t), wherein an average transmission power of the 16-QAM modulation signal s2(t) being the same as an average transmission power of the QPSK modulation signal s1(t), and (iv) transmits the transmission signal z1(t) from a first antenna at a first time and a first frequency and the second transmission signal z2(t) from a second antenna at the first time and the first frequency.

Abstract: A method executable by a low voltage drive circuit (LVDC) includes receiving an analog receive signal, converting the analog receive signal into analog inbound data, converting the analog inbound data into digital inbound data, filtering the digital inbound data to produce filtered digital data, sampling and holding an n-bit digital value of the filtered digital data to produce an n-bit sampled digital data value, adjusting formatting of the n-bit sampled digital data value to produce a formatted digital value, and generating a packet of received digital data from a plurality of formatted digital values.

Abstract: Various embodiments provide for a data sampler with built-in decision feedback equalization (DFE) and offset cancellation. For some embodiments, two or more data samplers described herein can be used to implement a data signal receiver circuit, which can use those two or more data samplers to facilitate half-rate or quarter-rate data sampling.

Abstract: A bidirectional isolated communication circuit and method for a differential signal. The circuit comprises a first detection circuit used for receiving a first differential pair from a first direction, converting the first differential pair into a first level signal, and inhibiting common-mode interference; a second detection circuit used for receiving a second differential pair from a second direction, converting the second differential pair into a second level signal, and inhibiting common-mode interference; an isolation adjustment circuit used for being provided between the first detection circuit and the second detection circuit and performing communication isolation; and a watchdog circuit used for being awoken according to the first differential pair and/or the second differential pair, and enabling the bidirectional isolated communication circuit to enter from a small current working mode to a normal working mode to perform communication isolation.

Abstract: A method for transmitting data via a coaxial electrical cable includes (a) converting symbols of each input data stream of a plurality of parallel input data streams from digital form to analog form, (b) individually filtering symbols of each input data stream, (c) transforming symbols of each input data stream from a first frequency-domain to a first time-domain, to generate parallel first time-domain samples, (d) converting the first time-domain samples to a serial multi-carrier signal, and (e) injecting the multi-carrier signal onto the coaxial electrical cable.

Abstract: The present disclosure relates to a radio frequency assembly and an electronic device. The radio frequency assembly includes: a radio frequency transceiver module, a first antenna, a second antenna, a first duplexer, and a second duplexer; the radio frequency transceiver module is configured to transmit and receive radio frequency signals; the first antenna is configured to transmit a first transmission signal and receive a first primary reception signal; the first duplexer is configured to insulate the first transmission signal from the first primary reception signal; the second antenna is configured to transmit a second transmission signal and receive a second primary reception signal; the second duplexer is configured to insulate the second transmission signal from the second primary reception signal.

Abstract: A radio frequency module includes a transmit filter of Band A and Band B, a transmit amplifier, and a switch circuit and can perform CA using a transmit signal of Band A and a receive signal of Band B, a transmit band of Band B including a receive band of Band C. The switch circuit includes a switch switching connection between a common terminal and a first selection terminal, a switch switching connection between the common terminal and a second selection terminal, and a switch switching connection between the second selection terminal and a third selection terminal. The common terminal is connected to the transmit amplifier. The first selection terminal is connected to the transmit filter of Band A. The second selection terminal is connected to the transmit filter of Band B. The third selection terminal is connected to a receive path of Band C.

Abstract: Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a t-switch with gate shunting. One aspect is an apparatus including a first differential switch having a control input. The apparatus further includes a second differential switch coupled to the first differential switch, the second differential switch a control input. A shunt capacitor is coupled between a first output and a second output of the first differential switch, and a first input and a second input of the second differential switch. A first shunt switch having a control input, an input, and an output has the input and the output coupled to the control input of the first differential switch. A second shunt switch having a control input, an input, and an output, has the input and the output coupled to the control input of the second differential switch.

Abstract: The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range.

Abstract: Methods and devices are disclosed for amplifying radio signals between a terminal and an antenna or an antenna connection of a circuit having an amplification unit and a detector unit, which has signal branches designed for different frequency ranges, and a power detector. A transmission signal received by the terminal is divided into at least a first signal part and a second signal part. The first signal part is applied to the signal branches of the detector unit. A frequency range of the first signal part is determined by sequential application of the signal branches of the detector unit to the power detector for evaluating a power of the first signal part. For the second signal part, the signal routing in the amplification unit is adjusted based on the frequency range determined by the detector unit. At least the second signal part is amplified by the amplification unit.

Abstract: A method and apparatus of distortion compensation during data transmission uses an interweaved look-up table (ILUT) to mitigate residual signal distortions in a signal transmitted over a transmission link. The ILUT interweaves states across both an I and a Q tributary to calculate mean error and an extended symbol basis. As a result, the method works particularly well against two-dimensional distortions like nonlinearity, IQ-imbalance, and quadrature error. The method may be used for either pre-compensation when it is combined with k-means clustering in a transmitter or post-compensation when it is combined with maximum likelihood (ML) detection in a receiver.