Abstract: Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.

Abstract: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.

Abstract: A radio frequency module includes a transmit filter of Band A and Band B, a transmit amplifier, and a switch circuit and can perform CA using a transmit signal of Band A and a receive signal of Band B, a transmit band of Band B including a receive band of Band C. The switch circuit includes a switch switching connection between a common terminal and a first selection terminal, a switch switching connection between the common terminal and a second selection terminal, and a switch switching connection between the second selection terminal and a third selection terminal. The common terminal is connected to the transmit amplifier. The first selection terminal is connected to the transmit filter of Band A. The second selection terminal is connected to the transmit filter of Band B. The third selection terminal is connected to a receive path of Band C.

Abstract: An electronic device according to various embodiments of the present invention can comprise: a housing; a first antenna element positioned inside the housing or at a first position thereof; a second antenna element positioned inside the housing or at a second position separated from the first position thereof; and a wireless communication circuit positioned inside the housing and electrically coupled to the first antenna element and the second antenna element.

Abstract: A physical layer transceiver for a wireline channel medium includes a host interface to a host device, a line interface to the medium, encoding/decoding circuitry for interfacing between the host device and the medium, and adaptive filter circuitry coupled to the encoding/decoding circuitry. The adaptive filter circuitry includes a plurality of filter taps, each corresponding to a segment of the medium, and capable of being powered ON and OFF separately from each other filter tap. Adaptive control circuitry can power ON a first subset, fewer than all the filter taps, corresponding to segments distributed along the medium, monitor powered-ON filter taps for occurrence of interference events, and upon detection of an interference event at a particular segment to which a particular powered-ON filter tap corresponds, power ON one or more additional filter taps corresponding to one or more segments in a vicinity of the particular segment.

Abstract: A radio frequency module includes: a transmission power amplifier that includes a plurality of amplifying elements that are cascaded; and a module board on which the transmission power amplifier is mounted, the module board including a first principal surface and a second principal surface on opposite sides of the module board. The plurality of amplifying elements include: a first amplifying element mounted on the first principal surface; and a second amplifying element mounted on the second principal surface and disposed upstream on a signal path from the first amplifying element.

Abstract: A radio frequency (RF) front end for wireless communications, in particular for use in a half duplex (HD) and/or full duplex (FD) transceiver. The RF front end is based on a quadrature balanced power amplifier (QBPA). The RF front end includes an antenna port for outputting a transmit signal to and receiving a receive signal from an antenna, and a receive port for outputting the receive signal to a signal processing section. Further, the QBPA is configured to receive a transmit input signal at a first port, receive a cancellation input signal at a fourth port, and receive the receive signal at a second port coupled to the antenna port.

Abstract: A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.

Abstract: Disclosed is a method for uplink transmission and reception in a wireless communication system and an apparatus therefor. Specifically, a method for performing uplink transmission by a user equipment (UE) in a wireless communication system may comprise the steps of: receiving downlink control information (DCI) including sounding reference signal (SRS) resource indication (SRI) and precoding indication from a base station; and transmitting an uplink to the base station by applying precoding indicated by the precoding indication on an antenna port of an SRS transmitted within an SRS resource selected by the SRI.

Abstract: Methods, systems and storage medium for separating a target signal from noise are disclosed. A method comprises providing a plurality of input signals, each of the plurality of input signals comprising the target signal; synchronizing the plurality of input signals; and separating the plurality of synchronized input signals into the target signal and the noise.

Abstract: An intelligent backhaul radio that has an advanced antenna system for use in PTP or PMP topologies. The advanced antenna system includes a plurality of directional antenna arrays, wherein each directional antenna array includes a plurality of directional antenna sub-arrays, and wherein each directional antenna sub-array includes a plurality of directional antenna elements. At least one of the plurality of directional antenna arrays includes at least one first directional antenna sub-array, said first directional antenna sub-array including a first number of directional antenna elements. At least one of the plurality of directional antenna arrays includes at least one second directional antenna sub-array, said second directional antenna sub-array including a second number of directional antenna elements. The first number is different than the second number.

Abstract: Embodiments of the present disclosure relate to methods, apparatuses and computer program products for signal detection in a wireless communication system. A method implemented at a receiver device includes obtaining a set of received signals; determining a channel on which the set of received signals are transported; and detecting a set of transmitted signals from the set of received signals in an iterative manner based on the determined channel, a modulation mode for the set of transmitted signals, and the set of received signals, by using a gradient descent (GD) algorithm. Embodiments of the present disclosure may reduce computation complexity required in signal detection and/or improve detection performance.

Abstract: Methods, systems, and devices for wireless communications provide for identification of multiple antenna panels at a user equipment (UE), and determination of panel-specific capabilities for the multiple antenna panels. A UE may determine whether simultaneous communications using two or more antenna panels is supported. The UE may determine that simultaneous communications using two or more antenna panels is supported based on a predetermined rule that indicates such simultaneous communications are supported or unsupported. Whether simultaneous communications on multiple panels is supported may be dependent upon a capability of the UE. The UE may transmit panel-specific capabilities to the base station, that may be used by the base station for subsequent communications between the UE and the base station.

Abstract: Disclosed is a method for uplink transmission and reception in a wireless communication system and an apparatus therefor. Specifically, a method for performing uplink transmission by a user equipment (UE) in a wireless communication system may comprise the steps of: receiving downlink control information (DCI) including sounding reference signal (SRS) resource indication (SRI) and precoding indication from a base station; and transmitting an uplink to the base station by applying precoding indicated by the precoding indication on an antenna port of an SRS transmitted within an SRS resource selected by the SRI.

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.

Abstract: An advanced communication system is provided. The advanced communication system comprises generating a first signal with a polyphase coding based on a DFT spread OFDM with at least one CAZAC sequence in accordance with a configuration condition, applying a digital transmit beamforming to the generated first signal, converting the first signal to analog from digital, modulating the converted first signal with an energy source, emitting, using at least one energy emit element, the modulated first signal, detecting a second signal comprising at least a portion of the emitted first signal that is reflected from at least one object in a scene in a field-of-view, demodulating the detected second signal, converting the second signal to digital from analog, converting the converted second signal to a computational image, and generating a 3D image by applying coherent detection to the computational image. The first signal comprises a polyphase sequence.

Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

Abstract: A circuit for processing radio frequency signal includes a first path and at least one other second path; herein the first path includes at least one radio frequency amplification device; a first radio frequency current generated by parasitic capacitance of the at least one radio frequency amplification device flows through the at least one second path; the circuit for processing the radio frequency signal further includes at least one resonance module, a first end of each of the at least one resonance module is connected with the first path, and a second end of each of the at least one resonance module is connected with at least a part of second paths of the at least one second path; and the at least one resonance module is configured to generate a resonance current opposite to the first radio frequency current.

Abstract: Disclosed is a frequency selective limiter with a switched multiplexer filter bank having a plurality of filters coupled between antenna and receiver ports, wherein the switched multiplexer filter bank is configured to enable and disable selected ones of the plurality of filters in response to control signals. First detector circuitry is coupled to the antenna port and configured to detect signal voltage at the antenna port and generate a first detector voltage. Second detector circuitry is coupled to the receiver port and configured to detect signal voltage at the receiver port and generate a second detector voltage, and a digital controller is coupled between the first detector circuitry, the second detector circuitry, and a control interface, wherein the digital controller is configured to limit interfering signals by sending control signals to the switched multiplexer filter bank in response to the first detector voltage and the second detector voltage.

Abstract: Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.