Abstract: Arrangement for generating pulse code modulation values in a telephone set, comprising a microprocessor which includes a working store, in which the microprocessor and the working store are connected by a data bus and an address bus, further including an output circuit for outputting the pulse code modulation values, an output memory connected thereto for storing the pulse code modulation values to be output, the working store and the output memory being incorporated in a single memory circuit. The arrangement is preferably structured in such a way that it comprises an addressing device for generating, in response to the microprocessor's addressing of a random location of the output memory, an address of an output memory location to be read out.

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm.

Abstract: In a terminal coupled to a computer network, a circuit for compensating for the baseline wander of received digital signals. The terminal is AC coupled to the computer network by a coupling transformer. The received digital signal is summed with a correction signal. The resulting summed signal is input to a comparator. This comparator compares the summed signal to a predetermined baseline level. Thus, the output signal from the comparator is fixed at the baseline level. The correction signal is the difference between the summed signal and the output signal from the comparator. The correction signal is filtered and amplified before being fed back to the comparator.

Abstract: A digital radio communications system employs a digital information source for providing digital information such as message bits, a transmitter for transmitting encoded digital information into data symbols in a radio-frequency (RF) signal to a plurality of antennae which sense the transmitted RF signal. A post detection measure of signal quality, the signal-to-impairment ratio, (SIR), is utilized by the receiver to perform post detection combining of signals received by a plurality of antennae. The antennae are coupled to a receiver which for each received signal: digitizes the signal, determines phase angles of the digitized signal, converts the signal to unit vectors, determines a signal-to-impairment ratio (SIR) estimates .gamma..sup.j of the digitized signals. The SIR estimate .gamma..sup.j is weighted by combining weight computation element and multiplied by each unit vector to provide an in-phase is component and a quadrature component for each signal.

Abstract: In a data receiver (6) a detection means (10) is used for determining a symbol value from the received signal. For reducing the effect of cyclostationary noise signals, a number of simultaneously operating detectors (12, 14) are used which derive a sequence of symbols from the input signal sampled at different instants. On the basis of a reliability measure simultaneously derived by the detectors, the symbol sequence whose associated reliability measure expresses the greatest reliability is conveyed to the output of the receiver with the aid of selection means.

Abstract: A clock synchronization system is constituted by first and second clock generating sections. The first and second clock generating units are alternately set in current and spare use modes. The apparatus clock from one clock generating section in the current use mode is supplied to an external circuit. In each clock generating section, a state signal generating section receives a first state signal representing one of the modes, and outputs a second state signal representing a set mode opposite to the mode represented by the first state signal to the other clock generating section. A clock generating section generates a clock synchronized with the network sync signal.

Abstract: A recognizer system having a transmitter for transmitting and a receiver receiving a serial stream of bits that includes data bits and a predetermined bit pattern. The recognizer system recognizes the predetermined bit pattern. A bit of the serial stream of bits is directly inputted from the receiver into a memory due to a clock pulse on the memory. The memory is programmed with decision tree statements of a decision tree. A initial state value, stored in a latch, is also inputted, from the latch, into the memory, due to the clock pulse on the memory. A next state value is immediately outputted from the memory. The outputted next state value replaces the initial state value stored in the latch, due to a delayed clock pulse on the latch. The next state is available to the memory. A signal bit is also outputted from the memory to a user device for the digital data. The system continues until a predetermined bit pattern produces a final state of a decision tree out of the memory.

Abstract: A sampling phase detector for a data bit synchronizer produces a constant level in the absence of data bit transitions. Reference voltages are provided and a switch selects between these reference voltages to provide an output which changes only when a data bit is detected and otherwise remains at a constant level. A loop filter operates together with the sampling phase detector to provide the constant voltage output in the absence of data bit transitions.

Abstract: An adaptive timing recovery method and apparatus are disclosed. The present invention reduces the problems in connection with the conventional timing recovery by varying the gain of the band-edge filtering in inverse proportion to the available band-edge energy in the received signal. The non-linearized outputs from the "early-late" filter are first added together and then subtracted from a reference value. A small fraction of the result is subtracted from the filter gains of the two half-symbol-rate filters. Therefore, if the band-edge energy is small, then the sum of the non-linearized outputs is negative and the timing filter gain values are increased. If the band-edge energy is large, then the filter gains will be reduced.

Abstract: An amplitude modulation system. An input analog signal indicating audio, etc., is converted into a digital form and the low-order bits of the resultant digital signal are converted into analog form. The resultant analog signal is used to control a gain of an analog controlled amplifier. On the other hand, a plurality of digitally controlled amplifiers are selectively turned on/off in response to the value of the high-order bits of the digital signal. Carrier amplified by the analog controlled amplifier are combined with carriers amplified by the plurality of digitally controlled amplifiers. Comparatively rough amplitude constituents are provided by outputs of the plurality of digitally controlled amplifiers and comparatively fine amplitude constituents are provided by output of the analog controlled amplifier.

Abstract: A data synchronizer (10) for synchronizing data generated by a data source (16) at a first rate includes a first timer (22) for generating a first timing signal at the first rate. A first register (20) connected to the first timer (22) has an input connected to the data source (16). The first register (20) temporarily stores multi-bit data words from the date source (16). A second timer (26) generates a second timing signal at the second rate. A second register (24) connected to the second timer (26) has an input connected to an output of the first register (20). The second register (24) temporarily stores multi-bit data words from the first register (20). A synchronizer connected to the first and second timers (22, 26) generates a good data signal when the multi-bit data words from the first register (20) is available at an output of the second register (24).

Abstract: A symbol lock detector for an incoming coherent digital communication signal which utilizes a subcarrier modulated with binary symbol data, d.sub.k, and known symbol interval T by integrating binary values of the signal over nonoverlapping first and second intervals selected to be T/2, delaying the first integral an interval T/2, and either summing or multiplying the second integral with the first one that preceded it to form a value X.sub.k. That value is then averaged over a number M of symbol intervals to produce a static value Y. A symbol lock decision can then be made when the static value Y exceeds a threshold level .delta..

Abstract: A modem device enabling a single communication line to be shared by a plurality of terminal units, and needing no switching operation between the terminal units on transmission. In transmission, when a transmission-start request is supplied from a terminal unit of any channel, the state of the other channels are checked. If these other channels are all in idle state, a channel selecting signal for selecting the channel corresponding to the transmission-start request is turned on so as to couple the corresponding terminal unit to a modem section for starting the transmission. In reception, on the other hand, upon receiving a call, priority calling channel information having been set in a predetermined mode register is read out to turn on a channel selecting signal for selecting the channel indicated by that information. As a result, a terminal unit of the channel corresponding to the channel selecting signal is selected to enable the receiving operation.

Abstract: Data transfer between subsystems of an information handling system employing a multiple subsystem clock environment architecture, or between multiple information handling systems operating with different clock frequencies, is synchronized using a timing aligned multiple frequency synthesizer with a synchronization window decoder. A frequency generation circuit in circuit communication with a data synchronization circuit functions to produce a synchronized timing signal(s) to permit a central processing unit operating in one subsystem clock environment to function with a peripheral subsystem(s), such as a memory controller, operating in a different subsystem clock environment, or permits information handling systems operating with different clock frequencies to function with one another. Data transfer synchronization delays are reduced and mean-time-to-failure of signal synchronization accuracy is increased by eliminating metastability effects from the synchronization circuitry.

Abstract: An automatic equalizer has a circuit for sensing cable effects that generates a control signal for a variable equalizer. A digital signal from a transmission channel is input to the variable equalizer to produce an equalized digital signal as a function of the control signal. The equalized digital signal is input to the sensing circuit which detects over-shoot or under-shoot of transitions in the equalized digital signal and adjusts the control signal accordingly to produce a balance in the transitions.

Abstract: In a transmission system comprising a plurality of data transmission circuits connected through a transmission line to form a loop, a local transmission signal is transmitted from a selected one of the data transmission circuits to the other data transmission circuits through the transmission line to be returned back to the selected data transmission circuit. The selected data transmission circuit interrupts the local transmission signal by detecting an identification signal preassigned to the selected data transmission circuit in a signal selecting circuit and by putting a switch circuit into an off-state during the local transmission signal sent from the selected data transmission circuit.

Abstract: A communication control device includes (a) a rate adapting unit for inputting thereto a receive clock for receiving a signal and outputting the receive clock of which waveform is partially deformed; and (b) a receiver for receiving the signal based on the receive clock outputted from the rate adapting unit.

Abstract: A delay chain having a known number of delay elements providing various delayed outputs of its input, a first and a second register set, and preferably, an array of multiplexors, are provided to measure the frequency of a digital signal, and the high and low time of its period. The digital signal to be measured is provided to the delay chain as input. A first and a second sample of the various delayed outputs are taken at the beginning and the end of a known time period, and stored in the first and second registers, one delayed output per register bit. The sample results stored in the register sets are read out through the multiplexors, and used to determine the frequency of the digital signal being measured, and the high and low time of its period.

Abstract: A data transfer arrangement by which variable-rate data transfer can be effected between a modem and a synchronous data terminal has a plurality of terminal-connected accesses. Namely, the first access for receiving data from the terminal, a second access for supplying clock signals to the terminal which fix the rate of the received data, a third access for supplying data to the terminal, and a fourth access for supplying clock signals to the terminal which fix the rate of the supplied data. Further accesses are connected via the modem to the transmission line for transmission and reception of data thereon at a uniform rate. A variable rate clock generator supplies clock signals to the second access, the clock rate being adjusted in accordance with the rate at which data is to be received from the data terminal.

Abstract: A method of transmitting data from a base transceiver station or base station to a transcoder. Prior to transmission to the base station, the data is organized in streams of frames (T1, T2, T3). The streams are assembled into groups (G1, G2, G3), and the transmission of the data to the base station starts at the start of a stream of frames (T1, T2, T3). The method includes the following operations: after activation of a channel of the base station for reception of the data frames, the first stream of frames (T1, T2, T3) received on the channel by the base station is associated with a reference number within the corresponding group of frames (G1, G2, G3); and transmission of data by the base station to the transcoder is then delayed by an amount (R.sub.1/3, R.sub.2/3) depending on the reference number and the group of frames of the first stream of frames, whereby a continuous stream of data (A1, A2, A3) is transmitted by the base station to the transcoder.