Abstract: A digital synthesizer for record circuitry of, e.g., a VCR, is supplied with digital samples representing a video signal. A calculator stage, responsive to the digital samples calculates a sequence of pulse periods defining a pulse duration modulated signal that represents FM modulation of a carrier by the video signal. An output sample generating stage operates on the sequence of pulse periods for generating a sequence of digital output samples which is converted in a digital-to-analog converter to the FM modulated video signal for subsequent recording on tape.

Abstract: Demodulation is provided for a base station receiver in a cellular communication system by a demodulator having four data linked digital signal processors. An MLSE equalizer and maximal ratio combiner for diversity paths includes multiple components that are partitioned among the processors for pipelined execution with predetermined time ordering.

Abstract: A modulation and demodulation system which modulates and demodulates a signal in a main channel for main data and a secondary channel for secondary data obtained by frequency division and uses, upon demodulation, a frequency timing extracted from the secondary channel as a sampling timing for an analog to digital conversion device for the main channel. The modulation and demodulation system is improved in that it can rapidly restore, when a timing error occurs, a processing condition in which a normal timing is used, and comprises a demodulation device which includes a phase timing error detection device for detecting an error of phase timing information extracted from the main channel and a storage device for storing the phase timing information. When the phase timing error detection device detects the error of the phase timing information, the demodulation device performs demodulation processing of main data using the phase timing information stored in the storage device.

Abstract: In a synchronization system for use in a digital transmission system in which an encoded digital transmission signal at least part of bits of which have specific statistic characteristics is transmitted, a digital transmission signal received by a decoder within a digital transmission apparatus at a receiving end is subjected to a decoding processing in units of samples on the basis of a synchronous input signal.

Abstract: A serial-parallel converter is arranged to convert an information sequence into a plurality of bit sequences. Two convolutional encoders are provided which respectively receive bit sequences from the serial-parallel converter. Each of the two convolutional encoders outputs first and second bit sequences. First parallel-serial converter receives the first bit sequences and converts them into third bit sequence, while second parallel-serial converter receives the second bit sequences and converts them into fourth bit sequence. The third and fourth bit sequences are used to modulate two carriers with a phase difference of .pi./2 radians.

Abstract: In a level detector (17), a bias voltage is developed by a bias current to have a substantially constant difference irrespective of a temperature variation from a detected voltage produced by detecting a device output signal for use in TDM modulation. A control signal generator (19) calculates a substantially temperature independent difference digital value by subtracting a second digital value of the bias voltage from a first digital value of the detected voltage to produce an attenuation control analog level used in controlling a variable attenuator (11) which deals with a device input signal to produce an attenuator output signal with a desired value for use as the device output signal. Preferably, the detected and the bias voltages are amplified by a variable gain amplifier (35) controlled by a processor output signal.

Abstract: A data transmitting/receiving apparatus comprises a master clock signal and a slave clock signal which differ in phase with each other according to a basic clock signal. Serial data is input according to the produced master clock signal or slave clock signal, a protocol process is applied to the input serial data, and the serial data subjected to the protocol process is output according to the master clock signal or the slave clock signal. A start delimiter detecting signal is generated when a start delimiter indicating the first frame is detected in the input serial data and phases are exchanged between the master clock signal and the slave clock signal when there arises a shift on a bit boundary of the serial data when the start delimiter detecting signal is generated.

Abstract: A circuit for reducing the amount of instability in a pulse width modualtion circuit by providing a minimum amount of overdrive after the crossover point between a ramp and a voltage threshold level, and a constant amount of discharge time between the end on one ramp and the beginning of the next. Also, a feedback loop is privided to increase or decrease the slope to compensate for a decreasing or increasing amount of time between clock pulses, to maintain the duty cycle of the output when the clock frequency varies.

Abstract: An automatic gain control circuit produces a control voltage for a digital baseband line equalizer having a ternary output signal. The circuit includes a capacitor for storing a charge to produce the control voltage, a charge circuit for charging the capacitor if the amplitude of the ternary output signal exceeds a reference voltage, and a discharging circuit for discharging the capacitor only when the ternary output signal is at a non-zero level.

Abstract: A circuit for seamlessly printing data from a remote source that is arriving at a clock rate that is equal to the clock rate of the local data, but that has a different clock phase, due to the longer path used by the remote data. The circuit generates a number of local clock phases, compares these phases to the phase of the remote clock, and uses for both local and remote data the clock whose phase is nearest that of the remote clock.

Abstract: A digital frequency upconversion and downconversion scheme for receivers and transmitters enables high resolution downconversion and upconversion, respectively, with low phase noise. A digital signal processor (DSP) receives temperature measurement information from a temperature transducer associated with a reference oscillator, and also receives channel tuning and other information. The DSP adjusts the signal samples accordingly, without adjusting the operation of the oscillator. Additionally, the inventive filtering scheme, preferably implemented in an application specific integrated circuit (ASIC), receives digital filtering coefficient information, digital symbol timing phase control signals, and, in some cases, other information from the DSP. As a result, the scheme enables operation at 1 Hz resolution, with phase noise which is at least 33.5 dB down at 10 Hz in the case of downconversion, and at least 42 dB down at 10 Hz in the case of upconversion.

Abstract: This serial data receiving apparatus is intended to realize the receiving process of serial data having an inferior SN ratio with a simple arrangement and at low cost. A one-bit length of the serial data is divided into several blocks. The sampling data is input at the multiple points of each block by using a shift register built in a microcomputer. The data is temporarily held so that the data at the same number block of each block is accumulated for several bits. The accumulation of the data results in cancelling the noise components and leaving the original signal components. This overlapping type receiving system makes it possible to clarify the receiving phase of a preamble signal for bit synchronization and to establish the bit synchronization. Next, the sampling data signals are entered at the multiple points based on the resulting receiving timing and the logic value of the bit is determined according to the ratio of the number of values of "1" to "0" contained in the data.

Abstract: A method and apparatus for estimating the phase differential of a transmitted electromagnetic signal from the amplitude envelope of the signal. The apparatus includes a sampler, phase estimator and demodulator. The phase estimator uses a Hilbert transform or an approximation of the Hilbert transform to estimate the phase differential. The method may be applied to time domain or frequency domain signals. The phase differential is estimated by taking the differential of a function of the envelope, and applying the Hilbert transform to this differential. The resulting phase differential, after correction for sign ambiguity may be used to demodulate the received signal.

Abstract: A flow control method (200) is suitable for use with a synchronous modem (101). The modem clocks data signals (107) from the terminal under control of a clock signal (109) supplied by the modem. The clock signal operates at a clock rate. The modem stores the data signals in a buffer (111), and thereupon transmits the data signals to a channel, the channel operating at a channel rate. When the quantity of data signals stored in the buffer exceeds a maximum threshold, the modem removes the clock signal from the terminal, thereby interrupting the flow of data signals from the terminal. When the quantity of data signals stored in the buffer is less than a minimum threshold, the modem again applies the clock signal to the terminal, thereby restoring the flow of data signals from the terminal.

Abstract: A digital block receiver system, in a cellular/wireless FM radiotelephony system, receives and heterodyne a block of cellular/wireless receive channels to a very low block IF signal by analog processing. This block IF signal is applied to a precision high speed A/D converter and converted to a digitized time series. A window function is applied to the digitized time series and a high speed FFT is applied to frequency isolate the individual channels. The active channels are digitally processed by a DSP to recover the FM channel modulation.

Abstract: This patent application discusses a direct phase digitizing apparatus (303) for use in a radiotelephone (101). The direct phase digitizing apparatus (303) accepts a first analog signal (309) having a phase, a voltage range and a first frequency. First, the direct phase digitizer generates an estimated phase map (611) having a second frequency and N-bits of resolution. Second, the direct phase digitizer detects a predetermined-voltage crossing (409) of the first analog signal (309). Third, using the predetermined-voltage crossings, the direct phase digitizer samples the estimated phase map. Fourth, a digital phase signal (623) is generated using the samples of the estimated phase map.

Abstract: A digital FSK transmitter utilizing a clock feedback signal driving an accumulator to operate a pair of registers having a pair of preset numbers stored therein to selectively add said numbers through a binary adder to the accumulator to output the FSK signal thereby.

Abstract: A modulation circuit includes a mapping position detector as well as a circuit for differentially phase coding a plurality of separated data streams. The differentially phase coding circuit is adapted to differentially phase code the plurality of data streams for each pulse time and generate a coded signal containing amplitude information. The mapping position detector detects the phase mapping position of the coded signal based on the amplitude information in the coded signal which is output from the differentially phase coding circuit. Information representing the detected phase mapping position is supplied to the differentially phase coding circuit so as to achieve a differential phase coding at a pulse time following one pulse time.

Abstract: A method and apparatus are provided for maximum likelihood sequence estimation. The method and apparatus includes a first maximum likelihood sequence estimator signal path for flat fading and an at least second maximum likelihood sequence estimator signal path for other than flat fading. The method and apparatus for further includes selecting the signal path with a least relative magnitude mean square error.

Abstract: The invention relates to a clock slip or drift counting process and apparatus, particularly for 2 Mbit MIC links consisting of using two detection modules (30,40) for frame locking words functioning as relays for incrementing a clock slip counter (80) on the basis of fixed frame locking loss and resumption criteria.