Patents Examined by Yu Chen
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Patent number: 11886990Abstract: A classification device includes a generation unit, a learning unit, a classification unit, and an output control unit. The generation unit generates pseudo data having a feature similar to a feature of training data. The learning unit learns, by using the training data and the pseudo data, a classification model that classifies data into one of a pseudo class for classifying the pseudo data and a plurality of classification classes other than the pseudo class and that is constructed by a neural network. The classification unit classifies, by using the classification model, input data as a target for classification into one of the pseudo class and the plurality of classification classes. The output control unit outputs information indicating that the input data classified into the pseudo class is data not belonging to any of the plurality of classification classes.Type: GrantFiled: March 8, 2019Date of Patent: January 30, 2024Assignee: Kabushiki Kaisha ToshibaInventor: Kouta Nakata
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Patent number: 11887916Abstract: In one example, an electronic device includes a substrate with a conductive structure and a substrate encapsulant. The conductive structure has a lead with a lead via and a lead protrusion. The lead via can include via lateral sides defined by first concave portions and the lead protrusion can include protrusion lateral sides defined by second concave portions. The substrate encapsulant covers the first concave portions at a first side of the substrate but not the second concave portions so that the lead protrusion protrudes from the substrate encapsulant at a second side of the substrate. An electronic component can be adjacent to the first side of the substrate and electrically coupled to the conductive structure. A body encapsulant encapsulates portions of the electronic component and the substrate. In some examples, the lead can further include a lead trace at the second side of the substrate. In some examples, the substrate can include a redistribution structure at the first side of the substrate.Type: GrantFiled: September 9, 2020Date of Patent: January 30, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Hyeong Il Jeon, Gi Jeong Kim, Yong Ho Son, Byong Jin Kim, Jae Min Bae, Seung Woo Lee
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Patent number: 11886987Abstract: A multiply-accumulate method and architecture are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally modulates the equivalent conductance of individual networks among the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network. A first partial selection of weights within the neural network is mapped into the equivalent conductances of the networks in the columns to enable the computation of multiply-and-accumulate operations by mixed-signal computation. The logic updates the mappings to select a second partial selection of weights to compute additional multiply-and-accumulate operations and repeats the mapping and computation operations until all computations for the neural network are completed.Type: GrantFiled: June 25, 2019Date of Patent: January 30, 2024Assignee: Arm LimitedInventors: Shidhartha Das, Matthew Mattina, Glen Arnold Rosendale, Fernando Garcia Redondo
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Patent number: 11880767Abstract: Embodiments of the present invention provide the use of a conditional Generative Adversarial Network (GAN) to simultaneously correct and downscale (super-resolve) global ensemble weather or climate forecasts. Specifically, a generator deep neural network (G-DNN) in the cGAN comprises a corrector DNN (C-DNN) followed by a super-resolver DNN (SR-DNN). The C-DNN bias-corrects coarse, global meteorological forecasts, taking into account other relevant contextual meteorological fields. The SR-DNN downscales bias-corrected C-DNN output into G-DNN output at a higher target spatial resolution. The GAN is trained in three stages: C-DNN training, SR-DNN training, and overall GAN training, each using separate loss functions. Embodiments of the present invention significantly outperform an interpolation baseline, and approach the performance of operational regional high-resolution forecast models across an array of established probabilistic metrics.Type: GrantFiled: February 21, 2022Date of Patent: January 23, 2024Assignee: ClimateAI, Inc.Inventors: Ilan Shaun Posel Price, Stephan Rasp
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Patent number: 11869117Abstract: A hybrid ray tracing system includes: a processor; and memory including instructions that, when executed by the processor, cause the processor to: identify a subset of pixels of an image to be ray-traced based on variable rate shading (VRS) screenspace image data; set, based on the VRS screenspace image data, one or more material properties of at least one object corresponding to the subset of pixels; and perform ray-tracing for the subset of pixels to generate a ray-traced image. The ray-tracing includes performing a limited ray casting process based on the set one or more material properties.Type: GrantFiled: January 14, 2022Date of Patent: January 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Keshavan Varadarajan, David C. Tannenbaum
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Patent number: 11861811Abstract: A neural network-based rendering technique increases temporal stability and image fidelity of low sample count path tracing by optimizing a distribution of samples for rendering each image in a sequence. A sample predictor neural network learns spatio-temporal sampling strategies such as placing more samples in dis-occluded regions and tracking specular highlights. Temporal feedback enables a denoiser neural network to boost the effective input sample count and increases temporal stability. The initial uniform sampling step typically present in adaptive sampling algorithms is not needed. The sample predictor and denoiser operate at interactive rates to achieve significantly improved image quality and temporal stability compared with conventional adaptive sampling techniques.Type: GrantFiled: September 8, 2022Date of Patent: January 2, 2024Assignee: NVIDIA CorporationInventors: Carl Jacob Munkberg, Jon Niklas Theodor Hasselgren, Anjul Patney, Marco Salvi, Aaron Eliot Lefohn, Donald Lee Brittain
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Patent number: 11860572Abstract: Examples are disclosed that relate to computing devices, head-mounted display devices, and methods for displaying holographic objects using slicing planes or volumes. In one example a computing device causes a display system to display a holographic object associated with a holographic volume, the holographic object occluding an occluded holographic object that is not displayed. Location data of at least a portion of a hand is received from a sensor. The location data of the hand is used to locate a slicing plane or a slicing volume within the holographic volume. Based on the location of the slicing plane or the slicing volume, at least a portion of the occluded holographic object is displayed via the display system.Type: GrantFiled: November 15, 2022Date of Patent: January 2, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Addison Kenan Linville, Jarod Wayne Lenz Erwin, Dong Yoon Park
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Patent number: 11862540Abstract: A frame includes leadframe units arranged in a matrix. Each leadframe unit has a die pad and tie bars connected to and extending from the die pad. Each tie bar includes an internal tie bar portion and an external tie bar portion. The internal tie bar portion of at least one tie bar includes a cut separating a part of the internal tie bar portion from the external tie bar portion. An out-of-plane bend in that part forms a mold flow control structure.Type: GrantFiled: February 2, 2021Date of Patent: January 2, 2024Assignee: STMicroelectronics SDN BHDInventor: Yh Heng
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Patent number: 11861500Abstract: A meta-learning system includes an inner function computation module, adapted to compute output data from applied input data according to an inner model function, depending on model parameters; an error computation module, adapted to compute errors indicating mismatches between the computed output data and target values; a state update module, adapted to update the model parameters of the inner model function according to an updated state, updated based on a current state of the state update module, in response to an error received from the error computation module. The state update module is learned to adjust the model parameters of the inner model function, such that a following training of the inner model function with training data is improved.Type: GrantFiled: December 19, 2018Date of Patent: January 2, 2024Assignee: SIEMENS HEALTHCARE GMBHInventor: Martin Kraus
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Patent number: 11861776Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for providing personalized avatars for virtual companionship are disclosed. One of the methods includes capturing one or more current online activities of a user of an online education platform providing learning services to the user; receiving sensor data from one or more electronic devices of the user; detecting an event by analyzing a combination of the one or more captured online activities of the user and the received sensor data; determining one or more avatars and one or more special effects associated with the one or more avatars based on the detected event and one or more pre-determined rules mapping avatars and special effects to events; generating multimedia content comprising the one or more avatars and the one or more special effects; and streaming the generated multimedia content to a multimedia display device of the user.Type: GrantFiled: November 19, 2021Date of Patent: January 2, 2024Assignee: Chegg, Inc.Inventor: Vincent Le Chevalier
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Patent number: 11853879Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating document vector representations. One of the methods includes obtaining a new document; and determining a vector representation for the new document using a trained neural network system, wherein the trained neural network system has been trained to receive an input document and a sequence of words from the input document and to generate a respective word score for each word in a set of words, wherein each of the respective word scores represents a predicted likelihood that the corresponding word follows a last word in the sequence in the input document, and wherein determining the vector representation for the new document using the trained neural network system comprises iteratively providing each of the plurality of sequences of words to the trained neural network system to determine the vector representation for the new document using gradient descent.Type: GrantFiled: July 26, 2019Date of Patent: December 26, 2023Assignee: Google LLCInventor: Quoc V. Le
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Patent number: 11853875Abstract: A processor-implemented neural network method includes acquiring connection weight of an analog neural network (ANN) node of a pre-trained ANN; and determining, a firing rate of a spiking neural network (SNN) node of an SNN, corresponding to the ANN node, based on an activation of the ANN node which is determined based on the connection weight. and the firing rate is also determined based on information indicating a timing at which the SNN node initially fires.Type: GrantFiled: October 23, 2018Date of Patent: December 26, 2023Assignees: Samsung Electronics Co., Ltd., UNIVERSITAET ZUERICHInventors: Bodo Ruckauer, Shih-Chii Liu
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Patent number: 11853886Abstract: In a computer system that includes a trained recurrent neural network (RNN), a computer-based method includes: producing a copy of the trained RNN; producing a version of the RNN prior to any training; trying to solve a control task for the RNN with the copy of the trained RNN and with the untrained version of the RNN; and in response to the copy of the trained RNN or the untrained version of the RNN solving the task sufficiently well: retraining the trained RNN with one or more traces (sequences of inputs and outputs) from the solution; and retraining the trained RNN based on one or more traces associated with other prior control task solutions, as well as retraining the RNN based on previously observed traces to predict environmental inputs and other data (which maybe consequences of executed control actions).Type: GrantFiled: September 30, 2022Date of Patent: December 26, 2023Assignee: Nnaisense SAInventor: Hans Jürgen Schmidhuber
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Patent number: 11853910Abstract: Provided are a computer program product, system, and method for ranking action sets comprised of actions for an event to optimize action set selection. Information is maintained on actions for a plurality of events. Each action indicates an action value of the action to the user and event weights of the action with respect to a plurality of the events. A determination is made of actions sets having at least one action to perform for the event. For each determined action set, a rank of the action set is calculated as a function of the action value for each action in the action set and an event weight of the action with respect to the event. At least one action set is presented to the user for consideration. In response to receiving user feedback, an adjusted rank is set for at least one of the presented action sets.Type: GrantFiled: October 17, 2019Date of Patent: December 26, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORTIONInventors: Tansel Zenginler, Natalie Brooks Powell, Vinod A. Valecha
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Patent number: 11847553Abstract: Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.Type: GrantFiled: June 14, 2018Date of Patent: December 19, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy, Jun Sawada, John V. Arthur, Dharmendra S. Modha, Steven K. Esser, Brian Taba, Jennifer Klamo
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Patent number: 11848375Abstract: An IGBT chip having a ?-shape mixed gate structure includes a plurality of mixed gate units. Each of the mixed gate units includes a gate region and two active regions located at two sides of the gate region. The gate region includes a trench gate and a planar gate that is located on a surface of the gate region, and the planar gate is connected with the trench gate and formed a ?-shape mixed structure. In this way, the IGBT chip can have a significantly improved chip density, while retaining features of low power consumption and high current density of the trench gate and a feature of a wide safe operating area of the planar gate.Type: GrantFiled: September 18, 2018Date of Patent: December 19, 2023Assignee: ZHUZHOU CRRC TIMES ELECTRIC CO., LTDInventors: Guoyou Liu, Chunlin Zhu, Liheng Zhu
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Patent number: 11830919Abstract: The present application discloses a method for fabricating a semiconductor device with a flat surface. The method for fabricating a semiconductor device including providing a substrate, forming a gate structure on the substrate, and forming a plurality of word lines having top surfaces at a same vertical level as a top surface of the gate structure.Type: GrantFiled: October 22, 2021Date of Patent: November 28, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11824112Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; third and fourth electrodes inside a trench of the semiconductor part, the fourth electrode being provided between the first electrode and the third electrode; a first insulating portion electrically insulating the third electrode from the semiconductor part; a second insulating portion electrically insulating the third electrode from the second electrode; a third insulating portion electrically insulating the fourth electrode from the semiconductor part; a fourth insulating portion electrically insulating the fourth electrode from the third electrode; and a fifth insulating portion including a first portion and a second portion, the first portion being provided inside the fourth electrode, the second portion extending outward of the fourth electrode.Type: GrantFiled: July 14, 2022Date of Patent: November 21, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Toshifumi Nishiguchi
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Patent number: 11823024Abstract: The present disclosure provides directed to new, more efficient neural network architectures. As one example, in some implementations, the neural network architectures of the present disclosure can include a linear bottleneck layer positioned structurally prior to and/or after one or more convolutional layers, such as, for example, one or more depthwise separable convolutional layers. As another example, in some implementations, the neural network architectures of the present disclosure can include one or more inverted residual blocks where the input and output of the inverted residual block are thin bottleneck layers, while an intermediate layer is an expanded representation. For example, the expanded representation can include one or more convolutional layers, such as, for example, one or more depthwise separable convolutional layers. A residual shortcut connection can exist between the thin bottleneck layers that play a role of an input and output of the inverted residual block.Type: GrantFiled: July 22, 2021Date of Patent: November 21, 2023Assignee: GOOGLE LLCInventors: Andrew Gerald Howard, Mark Sandler, Liang-Chieh Chen, Andrey Zhmoginov, Menglong Zhu
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Patent number: 11823324Abstract: A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, includes geometry processing logic having geometry transform and sub-primitive logic configured to receive graphics data of input graphics data items, and to determine transformed positions within the rendering space of one or more sub-primitives derived from the input graphics data items using a plurality of shader stages; and a tiling unit configured to generate control stream data including sub-primitive indications to indicate which of the sub-primitives are to be used for rendering each tile. The geometry processing logic is configured to write to a memory, for each instance of a pre-determined shader stage, shader stage output data comprising data output from each instance of the pre-determined shader stage used to process the received graphics data.Type: GrantFiled: January 24, 2022Date of Patent: November 21, 2023Assignee: Imagination Technologies LimitedInventors: Xile Yang, John W. Howson