Patents Examined by Yu-Hsi D Sun
-
Patent number: 12136687Abstract: A quantum dot composite includes a matrix and a plurality of quantum dots dispersed in the matrix, and a color conversion panel and a display panel including the same. The plurality of quantum dots include a metal including indium (In) and zinc and a non-metal including phosphorous (P), selenium, and sulfur, wherein the plurality of quantum dots includes a mole ratio of sulfur to indium of greater than or equal to about 3:1 and less than or equal to about 6:1, and a mole ratio of sulfur to selenium of greater than or equal about 0.69:1 and less than or equal to about 0.89, and a mole ratio of zinc to indium of greater than or equal to about 10:1 and less than or equal to about 12.4:1, and wherein the plurality of the quantum dots are configured to emit red light.Type: GrantFiled: January 28, 2022Date of Patent: November 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Garam Park, Shang Hyeun Park, Min Jong Bae, Mi Hye Lim, Deukseok Chung, Shin Ae Jun
-
Patent number: 12132095Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.Type: GrantFiled: March 31, 2023Date of Patent: October 29, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
-
Patent number: 12132022Abstract: The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device comprises: a semiconductor substrate; a passivation layer, arranged on an upper surface of the semiconductor substrate; a protective layer, arranged on an upper surface of the passivation layer, a dummy opening being formed on the protective layer; and, a dummy bump, partially located in the dummy opening and closely attached to the protective layer.Type: GrantFiled: March 8, 2021Date of Patent: October 29, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zengyan Fan
-
Patent number: 12125816Abstract: A semiconductor device assembly is provided. The assembly includes a redistribution layer (RDL) including a plurality of external contacts on a first side and a plurality of internal contacts on a second side opposite the first side. The assembly further includes a first die at least partially embedded in the RDL and having an active surface between the first side and the second side of the RDL. The assembly further includes one or more second dies disposed over the controller die and the RDL, wherein the one or more second dies electrically coupled to the internal contacts. The assembly further includes an encapsulant at least partially encapsulating the one or more second dies.Type: GrantFiled: June 9, 2021Date of Patent: October 22, 2024Assignee: Micron Technology, Inc.Inventors: Jong Sik Paek, Po Chih Yang
-
Patent number: 12125915Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes forming, over a substrate, a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess that extends into the substrate and exposes a portion of the substrate, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively forming a buffer semiconductor layer on the exposed portion of the substrate, selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layer and the buffer semiconductor layer such that a top surface of the buffer semiconductor layer is completely covered by the first epitaxial layer, and depositing a second epitaxial layer over the first epitaxial layer and the inner spacers.Type: GrantFiled: January 21, 2022Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shahaji B. More, Cheng-Han Lee
-
Patent number: 12108640Abstract: Provided is an array substrate, including: a first conductive wire, a second conductive wire and a first electrostatic protection unit, wherein the first electrostatic protection unit comprises a first thin-film transistor and a first capacitor; wherein a gate of the first thin-film transistor is suspended and is connected to a first electrode of the first thin-film transistor via the first capacitor, the first electrode of the thin-film transistor is connected to the first conductive wire, and a second electrode of the first thin-film transistor is connected to the second conductive wire.Type: GrantFiled: November 3, 2020Date of Patent: October 1, 2024Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Hongfei Cheng, Xueguang Hao
-
Patent number: 12107070Abstract: Provided is a method for manufacturing a semiconductor device which connects a first bond point and a second bond point by a wire. The method includes: a ball bonding step in which a crimping ball and a ball neck are formed at the first bond point by ball bonding; a thin-walled portion forming step in which a thin-walled portion having a reduced cross-sectional area is formed between the ball neck and the crimping ball; a wire tail separating step in which after a capillary is raised to unroll a wire tail, the capillary is moved in a direction to the second bond point, and the wire tail and the crimping ball are separated in the thin-walled portion; and a wire tail joining step in which the capillary is lowered and a side surface of the separated wire tail is joined onto the crimping ball.Type: GrantFiled: July 15, 2020Date of Patent: October 1, 2024Assignee: SHINKAWA LTD.Inventors: Hiroaki Yoshino, Shinsuke Tei
-
Patent number: 12107077Abstract: A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.Type: GrantFiled: January 31, 2023Date of Patent: October 1, 2024Assignee: SK hynix Inc.Inventor: Tae Hoon Kim
-
Patent number: 12107194Abstract: Disclosed is a semiconductor light emitting device comprising a semiconductor light emitting chip having electrodes; a mold, which has a first surface roughness and includes a bottom portion where the semiconductor light emitting chip is arranged and through holes formed in the bottom portion, with the through holes being comprised of a surface having a second surface roughness different from the first surface roughness, wherein at least one side of the mold facing the semiconductor light emitting chip is made of a material capable of reflecting at least 95% of light emitted by the semiconductor light emitting chip; and conductive parts provided in the through holes for electrical communication with the electrodes.Type: GrantFiled: December 27, 2019Date of Patent: October 1, 2024Assignee: WAVELORD CO., LTD.Inventor: Sang Jeong An
-
Patent number: 12107073Abstract: A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.Type: GrantFiled: October 27, 2020Date of Patent: October 1, 2024Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Zhihua Sun, Yanping Liao, Seungmin Lee, Qiujie Su, Feng Qu, Yingmeng Miao, Xibin Shao
-
Patent number: 12100657Abstract: A semiconductor device and a method for forming a semiconductor device are provided. The method for forming a semiconductor device includes the following steps. A substrate is provided, in which the substrate has a periphery region, a jointing region and a device region adjoined in sequence. A metal layer is formed on an upper surface of the substrate. A dielectric layer is formed above the metal layer. An opening is formed in the dielectric layer, in which the opening is located above at least one of the periphery region or the jointing region so as to expose the metal layer to form a contact window, and a height of an upper surface of the metal layer exposed to the contact window is lower than a height of an upper surface of the metal layer located in the device region.Type: GrantFiled: August 25, 2021Date of Patent: September 24, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zhongming Liu
-
Patent number: 12096685Abstract: Disclosed is a persistent luminescence emitter containing an electron donor molecule and an electron acceptor molecule having a LUMO level of lower than ?3.5 eV, wherein emission intensity increases by temperature rise after photo-irradiation of the persistent luminescence emitter stops.Type: GrantFiled: February 1, 2022Date of Patent: September 17, 2024Assignee: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATIONInventors: Kazuya Jinnai, Ryota Kabe, Chihaya Adachi
-
Patent number: 12087716Abstract: Microelectronic devices may include first bond pads located proximate to, and distributed along, a first side of the microelectronic device. Other bond pads may be located proximate to, and distributed along, another side of the microelectronic device perpendicular to the first side. A first pitch of the first bond pads may be greater than another pitch of the other bond pads. When microelectronic devices are placed side by side, the bond pads on sides of the microelectronic devices proximate to one another may be interposed between one another in the direction parallel to the first shortest distance between adjacent first bond pads.Type: GrantFiled: December 21, 2021Date of Patent: September 10, 2024Assignee: Micron Technology, Inc.Inventors: Ken Ota, Saaya Izumi, Tomohiro Kitano
-
Patent number: 12089449Abstract: A display panel includes: a base; a pixel defining layer disposed on a side of the base; a plurality of light-emitting devices disposed on a side of the base; and at least one connection portion disposed on a side of the pixel defining layer away from the base. The pixel defining layer has a plurality of first openings. At least a portion of each light-emitting device is located in a first opening. An orthogonal projection of a connection portion on the base is located within an orthogonal projection of the pixel defining layer on the base. A surface of the connection portion away from the base has a plurality of protrusions, and the connection portion is configured to diffusely reflect external ambient light incident into the display panel.Type: GrantFiled: September 29, 2020Date of Patent: September 10, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Haitao Huang, Chuanxiang Xu, Shi Shu, Yong Yu, Renquan Gu
-
Patent number: 12080616Abstract: The subject application relates to reinforced semiconductor device packaging and associated systems and methods. The device generally includes a substrate and one or more integrated circuit dies electrically coupled to the substrate with wire bonds. The device includes an encapsulant enclosing the one or more dies and the wire bonds. The package can include a reinforcing layer positioned on one or more surfaces of the encapsulant, a reinforcing wire extending through the encapsulant, or entrained reinforcing fiber portions positioned throughout the encapsulant. The reinforcing layer can be textile woven from synthetic or natural fibers, such as aramid, carbon, or glass. The package can be formed by disposing a reinforcing textile layer in a mold, placing a die and substrate in the mold with a liquid encapsulant, and hardening the liquid encapsulant to adhere the reinforcing textile layer, the encapsulant, the die, and the substrate together.Type: GrantFiled: December 15, 2021Date of Patent: September 3, 2024Assignee: Micron Technology, Inc.Inventors: Suresh K. Upadhyayula, Yeow Chon Ong, Hong Wan Ng
-
Patent number: 12074143Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.Type: GrantFiled: July 27, 2022Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
-
Patent number: 12074178Abstract: An imaging device according to one embodiment of the present disclosure includes a first electrode, a second electrode, and a photoelectric converter. The first electrode includes an oxide semiconductor material having an amorphous state. The second electrode is opposed to the first electrode. The photoelectric converter is provided between the first electrode and the second electrode, and includes a compound semiconductor material.Type: GrantFiled: November 22, 2019Date of Patent: August 27, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Chigusa Yamane
-
Patent number: 12068261Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.Type: GrantFiled: August 29, 2022Date of Patent: August 20, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
-
Patent number: 12062625Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.Type: GrantFiled: September 30, 2021Date of Patent: August 13, 2024Assignee: SANDISK TECHNOLOGIES, INC.Inventors: Hope Chiu, Hua Tan, Kent Yang, Weiting Jiang, Jerry Tang, Simon Dong, Yuequan Shi, Rosy Zhao
-
Patent number: 12057413Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.Type: GrantFiled: April 24, 2019Date of Patent: August 6, 2024Assignee: Intel CorporationInventors: Lijiang Wang, Jianyong Xie, Arghya Sain, Xiaohong Jiang, Sujit Sharan, Kemal Aygun