Patents Examined by Yu-Hsi D Sun
  • Patent number: 11877461
    Abstract: Embodiments of the present disclosure provide a light emitting diode device, a display panel, a display device, and a manufacturing method.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: January 16, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenhai Mei, Yichi Zhang
  • Patent number: 11876039
    Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side with a coupling structure so that the first component terminals and the second component terminals face opposite directions. Interconnects are connected to the conductive structure. The second component terminals and the interconnects are configured for connecting to a next level assembly. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: June 11, 2022
    Date of Patent: January 16, 2024
    Assignee: Amkor Technol Singapore Holding Pte. Ltd.
    Inventors: Roger D. St. Amand, Louis W. Nicholls
  • Patent number: 11869824
    Abstract: A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Kyle J. Arrington, Aaron McCann, Kelly Lofgreen, Elah Bozorg-Grayeli, Aravindha Antoniswamy, Joseph B. Petrini
  • Patent number: 11869876
    Abstract: The present application discloses a thinning system in package featuring an encapsulation structure in which no printed circuit board exists and comprising: a plurality of dies mounted on a top face of a copper holder and electrically connected to the plurality of data pins on the copper holder; a passive element mounted on the top face and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder and both the dies and the passive element are fixed on the top face of the copper holder through a layer of insulation adhesives; a molding compound encasing the dies and the passive element on the top face of the copper holder.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 9, 2024
    Assignee: WALTON ADVANCED ENGINEERING INC.
    Inventors: Chun Jung Lin, Ruei Ting Gu
  • Patent number: 11869878
    Abstract: A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungseon Hwang, Wonyoung Kim, Jinchan Ahn
  • Patent number: 11862608
    Abstract: A semiconductor package includes a package substrate having a first insulating layer, a wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering at least a portion of the wiring layer, a pair of support members disposed to face each other on the second insulating layer of the package substrate, and a pair of semiconductor chips disposed between the pair of support members and electrically connected to the wiring layer, wherein the second insulating layer has an opening surrounding at least a portion of each of the pair of semiconductor chips.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jooyoung Oh
  • Patent number: 11849601
    Abstract: A display apparatus includes a substrate, a display portion that includes a plurality of pixels disposed on the substrate, and an encapsulation portion that covers the display portion and includes a hybrid encapsulation layer that includes a plurality of inorganic layers and at least one organic layer that includes a plasma polymer. An end of the hybrid encapsulation layer includes a tip portion that includes an inorganic material and a multi-layered portion which extends from the tip portion toward a central portion of the substrate and in which the plurality of inorganic layers and the at least one organic layer are sequentially and alternately stacked, and a thickness of each of the inorganic layers and the organic layer decreases toward the tip portion.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Choelmin Jang, Myungsoo Huh, Sunghun Key, Junggon Kim, Eun Jung
  • Patent number: 11848295
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: December 19, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
  • Patent number: 11848311
    Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventor: Bilal Khalaf
  • Patent number: 11848308
    Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wansoo Park, Sang Sub Song, Kyung Suk Oh
  • Patent number: 11842976
    Abstract: The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: December 12, 2023
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Hanlung Tsai, Chengchung Lin, Mingchih Chen
  • Patent number: 11842977
    Abstract: A semiconductor package includes a package substrate which includes a substrate base and a plurality of wiring patterns, a lower semiconductor chip, and an upper semiconductor chip. The substrate base includes a chip-accommodating cavity and the plurality of wiring patterns include a plurality of bottom wiring patterns on a bottom surface of the substrate base and a plurality of top wiring patterns on a top surface of the substrate base. The lower semiconductor chip is disposed in the chip-accommodating cavity and is connected to the plurality of bottom wiring patterns through a plurality of lower bonding wires. The upper semiconductor chip includes a first portion which is attached to the lower semiconductor chip and a second portion which overhangs the lower semiconductor chip.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 12, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jooyoung Oh
  • Patent number: 11837580
    Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11839101
    Abstract: A display substrate includes a display region and hollowed-out grooves provided at a periphery of the display region. The display substrate includes a first organic base layer, a light-emitting unit provided on the base structure layer and located at the display region; the first organic base layer is provided with a groove structure located between the hollowed-out grooves and the display region. The display substrate further includes a first inorganic package layer for covering the light-emitting unit and the groove structure.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: December 5, 2023
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Chengyuan Luo
  • Patent number: 11830853
    Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: November 28, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Nee Jang, Young Lyong Kim
  • Patent number: 11830942
    Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: November 28, 2023
    Assignee: Infineon Technologies LLC
    Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
  • Patent number: 11832537
    Abstract: The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of forming an electrode for a phase change memory device comprises forming over a semiconductor substrate an electrode comprising titanium silicon nitride (TiSiN) on a phase change storage element configured to store a memory state. Forming the electrode comprises exposing a semiconductor substrate to one or more cyclical vapor deposition cycles, wherein a plurality of the cyclical vapor deposition cycles comprises an exposure to a Ti precursor, an exposure to a N precursor and an exposure to a Si precursor.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 28, 2023
    Assignee: Eugenus, Inc.
    Inventors: Jae Seok Heo, Jerry Mack, Somilkumar J. Rathi, Niloy Mukherjee
  • Patent number: 11824036
    Abstract: A semiconductor device includes a printed circuit board having a plurality of first electrode pads on a first main surface and a plurality of second electrode pads electrically connected to at least one of the plurality of first electrode pads on a second main surface, a first chip disposed on the first main surface and having a non-volatile memory; a second chip having a third electrode pad and a control circuit configured to control an operation of the non-volatile memory, a dummy chip having a component that has a higher thermal conductivity than a substrate of the second chip, and a sealing member sealing the first, second, and dummy chips. The third electrode pad is connected to the component of the dummy chip via a first wiring, and the component of the dummy chip is connected to one of the plurality of first electrode pads via a second wiring.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 21, 2023
    Assignee: Kioxia Corporation
    Inventor: Akihiro Iida
  • Patent number: 11824043
    Abstract: A semiconductor package includes a base substrate, an insulating layer including a first region disposed on the base substrate and in which first and second openings are disposed and a second region, a remaining region of the base substrate other than the first region, a first semiconductor chip disposed on the base substrate and including bonding pads disposed closely to a first edge, at least one second semiconductor chip stacked on the first semiconductor chip in the form of a staircase toward a second edge, parallel to the first edge, and a molding portion covering the base substrate to encapsulate the first and second semiconductor chips, wherein the length of the first edge is disposed to overlap the second region, both ends of the second edge are disposed to overlap the first and second openings, and the molding portion fills the first and second openings.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Hyunjun Noh, Keunho Choi
  • Patent number: 11817377
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: November 14, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Fabien Quercia