Abstract: Embodiments of the present disclosure provide systems, methods, and computer storage media for providing data monitoring and analysis of a data center using an Entity-Component-System (ECS) architecture. Embodiments of the disclosure provide mechanisms for initializing the ECS architecture by associating devices and data metrics relating to the data center as entities and components. During runtime, the components are continuously updated with collected data metrics and the state of the entities are analyzed by the systems to determine if an event has occurred that requires a remedial action be performed. The events correspond to events occurring on the data center as they relate to the devices associated with the entities. Actions correspond to steps that are taken to rectify the event.

Abstract: In an embodiment, a processor may include a mesh network and a clock regulation circuit. The mesh network may include multiple mesh stops to operate based on a mesh clock signal. Each mesh stop may include a bandwidth counter to transmit a bandwidth count in response to a pulse of a synchronization signal. The clock regulation circuit may be to: receive a plurality of bandwidth counts from the plurality of mesh stops; aggregate the plurality of bandwidth counts to obtain an aggregated bandwidth value; determine a cycle stealing value based at least on a comparison of the aggregated bandwidth value to at least one threshold value; and gate the mesh clock signal based on the determined cycle stealing value. Other embodiments are described and claimed.

Abstract: Methods, systems, and apparatuses for configuring a device for a specific task or set of tasks thereby allowing the device to be used for more than one task or set of tasks while also enabling fine-grain control over how the device may be used. A device's file system can operate with a particular file system based on the task(s) that the device will perform. Further, the device can physically configure itself based on the task(s) that the device will perform.

Abstract: A computer boot method, performed by a processing device includes: reading a first bit string in a predetermined data block from a target device, performing a bit rotation in a first direction on the first bit string according to a first default bit count to generate a second bit string, obtaining a third bit string associated with a prestored bit string, determining whether a to-be-verified parameter of the second bit string matches the third bit string, authorizing the target device to perform a boot procedure when the to-be-verified parameter of the second bit string matches the third bit string, and not authorizing the target device to perform the boot procedure when the to-be-verified parameter of the second bit string does not match the third bit string.

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

Abstract: A chip power supply circuit and an electronic device are provided. The chip power supply circuit includes: one or more chips each comprising a first power supply pin and a second power supply pin; a first voltage regulator circuit connected to the first power supply pin of a corresponding chip of the one or more chips; and a second voltage regulator circuit, where the first power supply pin of the corresponding chip of the one or more chips is connected to the second power supply pin of the corresponding chip via the second voltage regulator circuit, and the second voltage regulator circuit is configured to convert the first voltage into a second voltage. The first voltage regulator circuit and the second voltage regulator circuit are respectively located on different sides of at least one of the one or more chips.

Abstract: The technology is generally directed to a coordinated power throttling mechanism for a payload using power provided by a rack such that the rack power does not exceed a threshold amount for greater than a predetermined period of time. The coordinated power throttling mechanism includes the rack providing a power throttling signal to the payload and the payload executing the power throttling upon detection of the throttling signal. The payload may detect the throttling signal and, after a delay, execute the power throttling. The delay may ensure that all payloads within the rack have detected the power throttling signal.

Abstract: [Object] To provide an information processing apparatus, an information processing method, and a program that are capable of improving the convenience of the communication connection to an external apparatus. [Solution] An information processing apparatus including: a control unit configured to detect an external apparatus in a wireless communication scheme, and perform control such that power ON request data is transmitted to the external apparatus in accordance with a detection result within a certain time from a detection processing start for the external apparatus, the power ON request data requesting the external apparatus to be powered on.

Abstract: An electronic device includes a first power input end, a second power input end, a detection circuit, and a power delivery controller. The first power input end is adapted for coupling to an alternating current adapter. The second power input end is adapted for coupling to a dual-role port device. The detection circuit is coupled to the first power input end and the second power input end. The power delivery controller is coupled to the detection circuit and configured to control the dual-role port device to switch from a source end to a sink end in response to the detection circuit detecting that the first power input end receives an adapter source voltage from the alternating current adapter and the second power input end bring to the dual-role port device.

Abstract: A BMC time management method, system and apparatus, and a computer medium are provided. The BMC time management apparatus includes a BMC, a CPU and a BIOS, wherein the BMC is configured to send time loss information to a CPU after detecting a loss of time of the BMC; the CPU is configured to send, after receiving the time loss information, a notification of executing a time recovery operation to the BIOS; and the BIOS is configured to obtain time information in a CMOS after receiving the notification of executing the time recovery operation, and synchronize the time information to the BMC, so that the BMC recovers the time of the BMC based on the time information.

Abstract: A voltage reference circuit included in a computer system includes an asymmetric amplifier circuit that includes two metal-oxide semiconductor field-effect transistors with different threshold voltages. The voltage reference circuit also includes an output circuit that generates, using a control signal, a bias signal and an output current that is used by a divider circuit to generate a reference voltage and a feedback voltage. The reference voltage and bias signal are used by the amplifier circuit to generate the control signal, which is based on a difference between the transistors' threshold voltages.

Abstract: There are provided techniques including a system, method, and computer-readable medium for clock drift monitoring and correction for autonomous vehicles. The method may include the steps of: determining that a first clock or a second clock of a vehicle is unable to synchronize with a common master clock of the vehicle according to a clock synchronization protocol, wherein the first clock and the second clock are associated with a first device and a second device of the vehicle respectively; and in response: determining a first value indicating a relative clock drift between the first clock and the second clock; determining a first time associated with data provided by the second device to the first device, the first time being determined according to the second clock; and determining a corrected first time according to the first clock based at least in part on the first value and the first time.

Abstract: There are provided techniques including a system, method, and computer-readable medium for clock drift monitoring and correction for autonomous vehicles. The method may include the steps of: determining that at least one of a first component associated with a first clock or a second component associated with a second clock of a vehicle is unable to synchronize with a common master clock of the vehicle according to a clock synchronization protocol; operating the first component or the second component without synchronization of the first clock or the second clock with the master clock; determining a first value indicating a relative clock drift between the first clock and the second clock; determining that the first value exceeds a first threshold value; and operating the vehicle in a degraded state or performing a mitigating action based at least in part on determining that the first value exceeds a first threshold value.

Abstract: Systems and methods for managing system protection settings with heterogeneous computing platforms are described. In an illustrative, non-limiting embodiment, an IHS may include a heterogeneous computing platform and a memory coupled to the heterogeneous computing platform, where the memory comprises a plurality of sets of firmware instructions, where each of the sets of firmware instructions, upon execution by a respective device among a plurality of devices of the heterogeneous computing platform, enables the respective device to provide a corresponding firmware service, and where at least one of the plurality of devices operates as an orchestrator configured to: receive context or telemetry data; and based, at least in part, upon the context or telemetry data, modify a setting of a feature selected from the group consisting of: Wake-on-Approach (WoA), and Walk away Lock (WaL).

Abstract: Methods and apparatus for dynamically controlling a quantum computer are described wherein the method includes selecting a first and second digital pulse signal stored in a memory, the first digital pulse signal having a first pulse shape and a first sample rate and the second digital pulse signal having a second pulse shape and a second sample rate, at least the first or the second sample rate being lower than an output sampling rate of a digital-to-analog converter (DAC); forming a digital pulse sequence signal, the forming including applying a first interpolation algorithm to determine a first upsampled digital pulse signal based on the first digital signal and a second interpolation algorithm to determine a second upsampled digital pulse signal based on the second digital signal, the sample rates of the first and second upsampled digital signals matching the sample rate of the DAC; and, providing the digital pulse sequence signal comprising the first and second upsampled digital pulse signals to an input

Abstract: An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.

Abstract: The present disclosure relates to an apparatus and a method for a real-time clock (RTC) module of a system-on-chip (SoC), and provides an apparatus for powering battery-powered RTC module of an SoC. The apparatus is integrated in the RTC module and comprises: a first regulator stage comprising one or more regulators, wherein the first regulator stage is configured to provide a core power supply voltage (VDD_CORE) on the basis of battery output voltage (VDD_BAT); and a crystal oscillator I/O unit, the crystal oscillator I/O unit being powered by the core power supply voltage (VDD_CORE) and an I/O power supply voltage (VDD_IO), wherein the apparatus directly provides the battery output voltage (VDD_BAT) as the I/O power supply voltage (VDD_IO).

Abstract: An abnormality detection circuit includes: a first current source configured to generate a first current flowing from an external terminal toward a reference potential terminal; a second current source configured to generate a second current flowing from a power supply potential terminal toward the external terminal; a comparator configured to generate an abnormality detection signal by comparing a detection voltage corresponding to an application voltage of the external terminal with a predetermined threshold voltage; and a controller configured to switch between a first abnormality detection mode in which an operation of generating the first current is performed and a second abnormality detection mode in which an operation of generating the second current is performed.

Abstract: An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.

Abstract: A first operating system and a second operating system are executed by a processor of a computing device. The first operating system has a first user space on which a first user space driver is executed. The second operating system has a second user space on which a second user space driver is executed. A common kernel driver is executed on a common kernel to determine which user space driver made a given function call to the common kernel driver and translate the given function call into a corresponding hardware-specific call, based on said determination. The common kernel driver enables the first user space driver and the second user space driver to access computer hardware of the computing device simultaneously.