Abstract: Methods and apparatus for dynamically controlling a quantum computer are described wherein the method includes selecting a first and second digital pulse signal stored in a memory, the first digital pulse signal having a first pulse shape and a first sample rate and the second digital pulse signal having a second pulse shape and a second sample rate, at least the first or the second sample rate being lower than an output sampling rate of a digital-to-analog converter (DAC); forming a digital pulse sequence signal, the forming including applying a first interpolation algorithm to determine a first upsampled digital pulse signal based on the first digital signal and a second interpolation algorithm to determine a second upsampled digital pulse signal based on the second digital signal, the sample rates of the first and second upsampled digital signals matching the sample rate of the DAC; and, providing the digital pulse sequence signal comprising the first and second upsampled digital pulse signals to an input

Abstract: An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.

Abstract: The present disclosure relates to an apparatus and a method for a real-time clock (RTC) module of a system-on-chip (SoC), and provides an apparatus for powering battery-powered RTC module of an SoC. The apparatus is integrated in the RTC module and comprises: a first regulator stage comprising one or more regulators, wherein the first regulator stage is configured to provide a core power supply voltage (VDD_CORE) on the basis of battery output voltage (VDD_BAT); and a crystal oscillator I/O unit, the crystal oscillator I/O unit being powered by the core power supply voltage (VDD_CORE) and an I/O power supply voltage (VDD_IO), wherein the apparatus directly provides the battery output voltage (VDD_BAT) as the I/O power supply voltage (VDD_IO).

Abstract: An abnormality detection circuit includes: a first current source configured to generate a first current flowing from an external terminal toward a reference potential terminal; a second current source configured to generate a second current flowing from a power supply potential terminal toward the external terminal; a comparator configured to generate an abnormality detection signal by comparing a detection voltage corresponding to an application voltage of the external terminal with a predetermined threshold voltage; and a controller configured to switch between a first abnormality detection mode in which an operation of generating the first current is performed and a second abnormality detection mode in which an operation of generating the second current is performed.

Abstract: An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.

Abstract: A first operating system and a second operating system are executed by a processor of a computing device. The first operating system has a first user space on which a first user space driver is executed. The second operating system has a second user space on which a second user space driver is executed. A common kernel driver is executed on a common kernel to determine which user space driver made a given function call to the common kernel driver and translate the given function call into a corresponding hardware-specific call, based on said determination. The common kernel driver enables the first user space driver and the second user space driver to access computer hardware of the computing device simultaneously.

Abstract: Shared function execution mitigates cold start penalties for execution units. When a serverless platform receives a request, the request is performed when the serverless platform has a warm execution unit for the request. If a warm execution unit is not available or running, the serverless platform may send the request to another serverless platform rather than cold start an execution unit. The cold start is performed when the warm execution unit is not available at other platforms.

Abstract: Systems and methods for transcribing collaboration session audio with heterogenous computing platforms are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a heterogeneous computing platform comprising a plurality of devices, and a memory coupled to the heterogeneous computing platform, where the memory comprises a plurality of sets of firmware instructions, where each set of firmware instructions, upon execution by a respective device, enables the respective device to provide a corresponding firmware service, and where at least one of the plurality of devices operates as an orchestrator configured to receive a collaboration policy and change a closed caption setting of a collaboration session based upon the collaboration policy.

Abstract: A resource scheduling method is provided. The energy storage device pool includes at least one energy storage device. One example method includes: receiving a resource scheduling application request, determining a target energy storage device from the energy storage device pool based on the resource scheduling application request, and allocating an electric power resource to a power consumption device by using the target energy storage device.

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.

Abstract: An expansion apparatus with a power management function includes a power supply device, an expansion module and a control module. The power supply device includes a controller and an output terminal, and provides a predetermined power through the output terminal. The expansion module includes an input port coupled to the output terminal, and multiple output ports operable to be coupled to multiple electronic apparatuses. The control module has a full-power output mode and a disabled mode, and receives a device identifier provided by the controller through the input port to learn the predetermined power, so as to selectively adjust the output ports to operate in the full-power output mode or the disabled mode based on the predetermined power, thereby limiting a total power consumed by the electronic apparatuses and the expansion module to be less than or equal to the predetermined power.

Abstract: A database system includes a plurality of computing devices. Each computing device includes a plurality of processing modules, a computing device operating system, and an application specific operating system. The computing device operating system includes a computing device operating system file system management instruction set. The application specific operating system includes at least one custom file system management instruction set operable to configure operation of a configurable set of processing modules of the plurality of processing modules based on generating a corresponding file system management configuration signal for each processing module of the configurable set of processing modules indicating a selected file system management instruction set of the computing device operating system or the application specific operating system.

Abstract: A power conversion device is provided, which includes: a power conversion circuit that performs power conversion between a primary power and a secondary power; a buffer data accumulation circuit that, in a predetermined buffer cycle, repeatedly acquires data sets relating to a state of the power conversion circuit and store the data sets in a ring buffer; a state monitoring circuit that generates a trigger signal in a case where a state of a predetermined monitoring target satisfies a predetermined condition; and a data replication circuit that, in a case where a trigger signal is generated, stores, in a data storage circuit, a plurality of the data sets accumulated in the ring buffer in a target storage period including a time before a generation time of the trigger signal.

Abstract: The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

Abstract: Introduced herein is a computer-implemented system for creating a digital twin of an electrical system using auto-discovery techniques. The system receives power data from meters in an electrical system. For each meter, the system captures a power profile related to a component connected to the meter and creates a set of delta data representing change in power over time. The system detects correlated changes by comparing the sets of delta data and generates a system dataset by combining the sets of delta data. The system detects echoes of power fluctuations of the electrical system from the system dataset and creates a digital twin of the electrical system.

Abstract: A method for inputting and/or outputting signals having a selectable sample rate in a time-synchronized manner on a group of input and/or output channels of an electronic circuit includes: configuring each channel of the group at a standard sample period; synchronously initiating all the channels of the group at the standard sample period; detecting an entry for a modified sample period TPeriod of a first channel of the group; detecting a current counter value TCounter; configuring the first channel at the modified sample period; establishing a waiting time of TWaiting clocks in accordance with TWaiting=TPeriod?mod(TCounter, TPeriod), where mod (TCounter, TPeriod) denotes the division remainder from the current counter value TCounter and the modified sample period TPeriod; and initiating the first channel after the waiting time TWaiting.

Abstract: The present disclosure provides intelligent radio frequency interference mitigation in a computing platform. The computing platform includes a processor, a memory, a system clock and a wireless network interface. The system clock can be controlled so that the processor and/or the memory may operate at a slow frequency or a fast frequency. The wireless network may operate on a radio channel that experiences radio frequency interference at the fast frequency. The system clock may be intelligently controlled to select the slow frequency to reduce radio frequency interference to prioritize execution of a network application, or to select the fast frequency to increase processor speed and prioritize execution of a local application.

Abstract: A distributed power network includes a power bus infrastructure distributed over a region with node points provided to interface with controllable power nodes. Each power node can be connected to an external power device such as a DC power sources, a DC power load, or a rechargeable DC battery. The power nodes form a communication network and cooperate with each other to receive input power from DC power sources and or rechargeable DC batteries connected to the power bus infrastructure and distribute the power received therefrom to the power bus infrastructure for distribution to the DC power loads and to rechargeable DC batteries.

Abstract: In an electronic device capable of running multiple software applications concurrently, applications, documents, cards, or other activities can be selected for hibernation so as to free up system resources for other activities that are in active use. A determination is made as to which activities should hibernate, for example based on a determination as to which activities have not been used recently or based on relative resource usage. When an activity is to hibernate, its state is preserved on a storage medium such as a disk, so that the activity can later be revived in the same state and the user can continue with the same task that was being performed before the activity entered hibernation.

Abstract: The example computing device includes a universal serial bus (USB) port to provide a data connection and power to a connected device. The example computing device also includes a controller to control a power state of the USB port during a reboot process of the computing device. The example computing device further includes a basic input/output system (BIOS) to send a port reboot setting to the controller. The port reboot setting defines a power-off time period that the USB port is to be powered off during the reboot process.