Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

Abstract: A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.

Abstract: A power management system and method for an SRAM circuit and an FPGA chip are provided. The power management system includes a power management, a power management controller and an oscillator. The power management circuit include a power-on reset circuit used to determine whether powering-on of a core voltage and an analog input-output voltage of power supply voltages of the power management circuit is completed. The power management controller and the oscillator are used to control the power management circuit to power on the SRAM circuit after the power-on reset circuit determines that the powering-on of the core voltage and the analog input-output voltage is completed, and further used to control the power management circuit to erase the SRAM circuit after the SRAM circuit is powered on. Powering-on sequences of various internal power supplies of the FPGA chip are clear, and power consumption of the FPGA chip can be reduced.

Abstract: The present disclosure describes automated generation of early warning predictive insights derived from contextual analysis of user activity data of a distributed software platform. Predictive insights are automatically generated from analysis of user activity through implementation of trained artificial intelligence (AI) modeling. User activity data is accessed pertaining to user interactions by a plurality of users a software data platform. The trained AI modeling generates a plurality of mobility determinations that identify changes in patterns of user behavior over a current temporal filter associated with the user activity data. The plurality of mobility determinations is curated using business logic rules that evaluate a relevance of the mobility determinations. One or more predictive insights may be generated and presented via a graphical user interface notification.

Abstract: Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

Abstract: During a boot process of a computing device, a boot loader loads a kernel and an initial RAM disk image from a persistent storage device into RAM. The initial RAM disk image includes a file system that includes a camera application. The kernel is invoked, and the kernel mounts a RAM disk from the initial RAM disk image as a root file system. The kernel causes an initiation of the camera application into a user space. The camera application obtains an image frame from a camera. The camera application processes the image frame to generate a processed image frame, and provides the processed image frame to a frame buffer for presentation of the processed image frame on a display device.

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Abstract: In one embodiment, a gaming system, method, and device may have a memory having a plurality of power management rules and a processor configured to receive a power status information from another device, retrieve at least one power management rule from the memory, and configure a power state of the gaming device or its peripheral device based on the power status information and the at least one power management rule.

Abstract: A method of operating a multiphase power supply includes identifying a least efficient phase of a plurality of phases in the multiphase power supply based on a comparison of a pulse width for each phase in the plurality of phases, and decreasing an amount of power supplied to a load by the identified least efficient phase.

Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.

Abstract: An information handling system may include a physical storage resource having a portion thereof that includes files that are usable during boot of the information handling system; at least one processor; and a Basic Input/Output System (BIOS) including instructions that are executable by the at least one processor for: during a boot process, determining whether any of a plurality of BIOS events have taken place during a previous boot process, wherein the plurality of BIOS events are indicative of malicious behavior during the previous boot process; and in response to a determination that at least a predetermined number of the plurality of BIOS events have taken place during the previous boot process, carrying out a remedial action during the boot process.

Abstract: Embodiments disclose a DEVS chip is used to send only meaningful data in the system and therefore saves energy and increase processing speed. The sensor nodes communicate with an office chip temperature sensor or power management. The data acquired by the senor nodes is used for evaluating of the quantizer which has a stored quantum size and a stored temperature value or power level. If the difference between a stored temperature or a stored power level and a new temperature or a new stored power level is greater or equal to the predetermined quantum size, the new temperature or new power level is saved. The quantizer generates an event that transmits the temperature or the power level with quantum value to the sensor nodes. The small changes in the difference does not affect the system beyond the quantizer.

Abstract: An information processing device includes a first information processing part having a first calculation part and a second information processing part having a second calculation part, which are communicated with each other. The first information processing part includes a first communication part and a first data storage part. The first calculation part is configured to execute a first communication device driver, a first periodic communication application, a first non-periodic communication application, and a first data processing application. The first data processing application integrates data which are read from a transmission periodic data list stored in the first data storage part with data which are read from a transmission non-periodic data list stored in the first data storage part to process into transmission integrated data, and the transmission integrated data are transmitted from the first communication part through execution of the first communication device driver.

Abstract: Embodiments disclose a DEVS chip is used to send only meaningful data in the system and therefore saves energy and increase processing speed. The sensor nodes communicate with an office chip temperature sensor or power management. The data acquired by the senor nodes is used for evaluating of the quantizer which has a stored quantum size and a stored temperature value or power level. If the difference between a stored temperature or a stored power level and a new temperature or a new stored power level is greater or equal to the predetermined quantum size, the new temperature or new power level is saved. The quantizer generates an event that transmits the temperature or the power level with quantum value to the sensor nodes. The small changes in the difference does not effect the system beyond the quantizer.

Abstract: A method for creating devices facilitating secure data transmission, storage and key management. At least two devices are each comprised of at least part of a physically unclonable function unit originally shared by the at least two devices on a single, monolithic original integrated circuit. The process includes physically segmenting the shared physically unclonable function unit between the at least two devices. The at least two devices which share the single, monolithic integrated circuit are physically separated into individual device units.

Abstract: A system, method and apparatus to authenticate an endpoint having a secure memory device. For example, at boot time of the endpoint, a cryptographic hash value of the boot loader stored in the memory device is used to generate a device identifier of the memory device; and identification data of multiple components of the endpoint is used with the device identifier of the memory device to generate a first key pair key and a second key. A counter value is retrieved from a monotonic counter to generate a certificate signed using a private key in the first key pair. The certificate can be sent over the computer network to a remote server for authentication using a public key in the first key pair. The second key pair can be authenticated and used to establish encryption for a communication connection between the endpoint and the server.

Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

Abstract: A vehicular device includes a CPU. The CPU is set in a rated state in which the CPU operates at a rated operating clock and a high speed state in which the CPU operates at an operating clock higher than the rated operating clock. The high speed state is changeable in the operating clock and the rated state is not changeable in the rated operating clock.

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.