Patents Examined by Zhou H. Li
  • Patent number: 11074189
    Abstract: Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ahmed Abulila, Vikram Sharma Mailthody, Zaid Qureshi, Jian Huang, Nam Sung Kim, Jinjun Xiong, Wen-Mei Hwu
  • Patent number: 10733114
    Abstract: Performance of a data cache is controlled; the cache implements a garbage collection process for maintaining free storage blocks in a data store of the cache and an eviction policy for selecting data to be evicted from the cache. A cache performance control method defines a performance target for operation of the cache and, in operation of the cache, monitors performance of the cache in relation to the performance target. The garbage collection process is selectively performed in a relocation mode and an eviction mode so as to promote compliance with the performance target. In the relocation mode, data contained in a set of storage blocks selected for garbage collection is relocated in the data store. In the eviction mode, a set of storage blocks for garbage collection is selected in dependence on the eviction policy and data contained in each selected storage block is evicted from the cache.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Antonios Kornilios Kourtis, Nikolas Ioannou, Ioannis Koltsidas
  • Patent number: 10423335
    Abstract: Systems and methods presented herein provide a controller is operable to increase a number of suspend operations during read Input/Output (I/O) operations of a storage device, and to detect an increase in response times for write commands due to the increased number of suspend operations. The controller is also operable to decrease the number of the suspend operations during the reads of the storage device to decrease the response times of the write commands.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 24, 2019
    Assignee: Seagate Technology LLC
    Inventors: David Scott Ebsen, Dana Simonson, Ryan James Goss
  • Patent number: 10101944
    Abstract: A data writing method for a solid state storage device is provided. The solid state storage device includes a flash memory with plural blocks. The data writing method includes the following steps. Firstly, a flush command is received. Then, host write data in a buffer are stored into an open block of the flash memory according to a program order. Then, a garbage collection is performed to acquire collected write data from a close block of the flash memory and temporarily store the collected write data into the buffer. Then, the host write data and the collected write data in the buffer are stored into the open block of the flash memory according to the program order.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 16, 2018
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Sheng-Jen Hsieh, Wei-Chi Hsu, Chung-Ming Su, Sen-Ming Chuang
  • Patent number: 8990504
    Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tara Astigarraga, Michael E. Browne, Joseph Demczar, Eric C. Wieder
  • Patent number: 8972647
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 7725658
    Abstract: A system and appertaining method provide for pre-fetching records from a central data base to a local storage area in order to reduce delays associated with the data transfers. User patterns for requesting data records are analyzed and rules/strategies are generated that permit an optimal pre-fetching of the records based on the user patterns. The rules/strategies are implemented by a routine that pre-fetches the data records so that users have the records available to them when needed.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: May 25, 2010
    Assignee: Siemens Aktiengesellschaft
    Inventors: Martin Lang, Ernst Bartsch
  • Patent number: 7640413
    Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: December 29, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Patent number: 7636828
    Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: December 22, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig VanZante, King Wayne Luk
  • Patent number: 7613866
    Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: November 3, 2009
    Assignee: Thomson Licensing
    Inventors: Tim Niggemeier, Thomas Brune
  • Patent number: 7596669
    Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: September 29, 2009
    Assignee: Broadcom Corporation
    Inventor: Joseph Herbst
  • Patent number: 7003622
    Abstract: A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at least the regular RAM or the redundant RAM according to an address applied thereto, and for reading data from a memory cell of the selected RAM specified by the address. A plurality of regular RAMs can be disposed and the redundant RAM includes redundant memory elements by which defective memory elements of an arbitrary one of the plurality of regular RAMs can be replaced. The control block selects either one of the plurality of regular RAMs or the redundant RAM according to an address applied thereto, and reads data from a memory cell of the selected RAM specified by the address.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hirofumi Shinohara, Yoshiki Tsujihashi, Takeshi Hashizume
  • Patent number: 6920521
    Abstract: A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the operating system stalls.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: July 19, 2005
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Sanjeev Ghai, Kenneth Lee Wright
  • Patent number: 6912637
    Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: June 28, 2005
    Assignee: Broadcom Corporation
    Inventor: Joseph Herbst
  • Patent number: 6868483
    Abstract: In a multiprocessor data processing system including: a main memory; at least first and second shared caches; a system bus coupling the main memory and the first and second shared caches; at least four processors having respective private caches with the first and second private caches being coupled to the first shared cache and to one another via a first internal bus, and the third and fourth private caches being coupled to the second shared cache and to one another via a second internal bus; method and apparatus for preventing hogging of ownership of a gateword stored in the main memory and which governs access to common code/data shared by processes running in at least three of the processors. Each processor includes a gate control flag. A gateword CLOSE command, establishes ownership of the gateword in one processor and prevents other processors from accessing the code/data guarded until the one processor has completed its use.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: March 15, 2005
    Assignee: Bull HN Information Systems Inc.
    Inventors: Wayne R. Buzby, Charles P. Ryan
  • Patent number: 6766417
    Abstract: An entertainment apparatus has a memory card, and an information processing unit to which the memory card is detachably connected. The memory card includes a flash ROM having identification information stored therein, and a ROM size table. The information processing unit is adapted to obtain page size information of the flash ROM from the identification information and the ROM size table and to control, in accordance with the obtained page size information, the reading and writing of data with respect to the flash ROM.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: July 20, 2004
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Makoto Tanaka, Yoichiro Fukunaga, Masaharu Yoshimori
  • Patent number: 6668308
    Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: December 23, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Patent number: 6636939
    Abstract: A memory interface unit is described having a first interface to receive a first request from a processor where the first request has an attribute. The memory interface unit also has a second interface to receive a second request from the processor where the second request does not have the attribute. The memory interface unit also has a third interface to read/write information from/to a system memory. A method is also described that involves forwarding a processor request along a first path to a memory interface unit if the request has one or more attributes; and forwarding the request along a second path to the memory interface unit if the processor request does not have the one or more attributes.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: October 21, 2003
    Assignee: Intel Corporation
    Inventor: Varghese George
  • Patent number: 6578109
    Abstract: A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: June 10, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Glen D. Stone, Scott D. Smyers, Bruce A. Fairman