Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.

Abstract: The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions, and memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. The memory access circuitry determines, according to a programmable mapping, a mapping of guard tag storage locations for storing guard tags for corresponding blocks of memory locations.

Abstract: A method is provided for operating a storage device having biometric security protection, including: simultaneously starting both a device initialization operation and a biometric recognition operation; and if the device initialization operation has completed and the biometric recognition operation has successfully completed, setting the storage device to a normal access mode permitting external access to the storage device in accordance with the biometric security protection, wherein the device initialization operation and the biometric recognition operation are performed concurrently.

Abstract: Systems and methods include storing one or more counters in a plurality of locations in Double Data Rate (DDR) Random Access Memory (RAM) such that each counter is stored partially in multiple locations across the DDR RAM; and accessing banks in the DDR RAM sequentially for read operations and write operations associated with the one or more counters. The multiple locations include a location in each bank of the banks in the DDR RAM. A read operation for a counter is performed by reading all of the corresponding multiple locations and combining associated values to return a result for the counter. A write operation for a counter is performed by writing to a location of the multiple locations that is currently in sequence.

Abstract: The present invention provides a control module and a control method thereof for an SDRAM. The control module includes at least one register and a controller. The controller is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operating mode; setting value of the at least one register under the DPIN operating mode; and control the SDRAM according to the value of the at least one register.

Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.

Abstract: Snapshots are processed without holding all write operations while the snapshots are being activated. Rather than holding all write operations until snapshots are activated, write operations may be allowed to proceed. Snapshot write processing may be temporarily suspended while the snapshots are being activated, including snapshot metadata being updated, while write operations received while the snapshots are being activated are logged. After snapshots have been activated for all logical LSUs for which snapshots were instructed to be activated, the logging of write operations may be stopped, and the logged write entries processed to determine whether any of the logged write operations require updating snapshot information of any logical storage elements (LSEs) of the LSUs. While the logged write operations are being processed, any write operations received from a host for an LSE having a logged write operation may be held until the held operation, or all held operations are processed.

Abstract: In a computer system, in a case where a throughput upper limit value is set as upper limit value 1, a throughput limit notification program executed by a storage device gives a notification to a storage management device when a throughput of a logical volume reaches the upper limit value 1. In response to this notification, a throughput upper limit value setting program executed by the storage management device outputs, to the storage device, a command for switching the throughput upper limit value from the upper limit value 1 to upper limit value 2, such that the throughput upper limit value is switched.

Abstract: A method of writing data in a storage device is provided. The method includes: receiving an identifier information request; outputting information indicating a plurality of identifiers based on the identifier information request; receiving a first write command and first data, the first write command comprising a first identifier among the plurality of identifiers; performing a data write operation on the first data based on the first write command; receiving a first attribute assignment command comprising the first identifier and a first attribute among a plurality of attributes; and assigning the first attribute to the first data that is already stored in the storage device based on the first attribute assignment command.

Abstract: An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.

Abstract: A data storage device may include a storage including a plurality of memory blocks composed of system memory blocks for storing system data and user memory blocks for storing user data; and a controller configured to: control exchange of the system and user data with the storage in response to a request of a host device; and determine whether a start condition for performing a garbage collection operation on the storage is satisfied, based on a number of bad memory blocks in the plurality of memory blocks.

Abstract: An amount of storage space required to maintain counter information for a storage system is reduced without reducing a temporal granularity or tracking granularity of the counter information. Rather than periodically recording actual (i.e., raw) counter values for counters, difference (i.e., delta) values may be recorded. For a given counter, a difference (delta value) between a value of the counter for a given point in time (PIT) and a value of the counter for a previous PIT may be determined, and this delta value may be stored as opposed to storing the raw counter value. This delta value may be a significantly smaller value than the raw value. To further reduce the amount of storage space required, no value may be stored for a counter for a given PIT if it is determined that there is no difference between a counter value for the given PIT and a previous PIT.

Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

Abstract: A method in one embodiment comprises separating logical block addresses of one or more storage devices of a storage system into a plurality of ranges of logical block addresses using a designated chunk size, the chunk size denoting a particular number of logical block addresses. The method further comprises assigning different ones of the ranges of logical block addresses to different ones of a plurality of cache entities of the storage system, to select paths for delivery of respective input-output operations from a host device to the storage system based at least in part on the assigning, detecting particular ones of the input-output operations that each overlap with two or more adjacent ranges of the plurality of ranges, and responsive to the detected input-output operations exceeding a threshold, modifying the chunk size and repeating at least portions of the separating, assigning, selecting and detecting utilizing the modified chunk size.

Abstract: A computer-implemented method according to one aspect includes receiving an indication of a track range to be released within a storage volume; identifying a data backup within a backup storage space for the storage volume that corresponds to the track range; and releasing the track range within the storage volume in response to determining that the corresponding data backup has expired within the backup storage space.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a controller. The PIM device includes a data storage region and an arithmetic circuit for performing an arithmetic operation for data outputted from the data storage region. The controller is configured to control the PIM device. The PIM device is configured to transmit arithmetic quantity data of the arithmetic circuit to the controller in response to a request of the controller.

Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.