Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

Abstract: This application provides a data reading method for a retrieval task and a retrieval apparatus. The method includes receiving a first retrieval task request, where the first retrieval task request corresponds to a first retrieval start address and a first retrieval end address in a target data area, and reading data for a first retrieval task starting from the first retrieval start address. The method includes receiving a second retrieval task request in a process of reading data for the first retrieval task. The method further includes obtaining an address of data to be read for the first retrieval task after receiving the second retrieval task request, and determining a second retrieval start address of a second retrieval task in the target data area based on the address of the data to be read. The method further includes reading data for the second retrieval task starting from the second retrieval start address.

Abstract: Processing circuitry processes instructions in one of at least three domains each associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request comprising a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment which caused the memory access request to be issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from among at least three partition identifier spaces based on a current domain of the processing circuitry).

Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

Abstract: Operation of a non-volatile memory (NVM) storage module may comprise receiving a plurality of commands as associated with a plurality of priority-based queues from a host-memory. A received command is evaluated in accordance with a priority associated with the queue storing the command and a size of the command. The evaluated command is split into a plurality of sub-commands, each of the sub-commands having a size determined in accordance with the evaluation. A predetermined number of hardware resources are allocated for each of the evaluated command based on at least the size of each of the sub-commands to thereby enable a processing of the evaluated command based on the allocated resources. Quality of service (QoS) for the evaluated-command may thus be augmented.

Abstract: A data storage device includes a shared command queue, a queue controller, a processor, and a memory. The command queue is configured to queue a plurality of jobs transmitted from a plurality of host processors. The queue controller is configured to classify the plurality of jobs into a plurality of levels of jobs according to priority threshold values and assign jobs of the plurality of levels of jobs the processor. The processor is configured to process the jobs assigned by the queue controller. The memory may store data needed to process the job.

Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a parent physical function (PF), receive one or more child PFs, determine whether any part of a first child command of a first child PF of the one or more child PFs can be executed prior to receiving approval from the parent PF, and start executing the first child command. The controller is further configured to initialize an indirect queue, set fetching pointers of the indirect queue to the first child command, mimic a doorbell for the first child command, fetch the first child command, determine whether the first child command has started execution by a child PF flow, and complete the first child command.

Abstract: A method of operating a storage means, wherein for writing and storing a storage item to the storage means the storage item to be written and stored—in particular by using the concept and theory of identification—is provided, a encoding process by means of randomization is applied to the storage item to generate and to provide a randomized encoded storage item, and the randomized encoded storage item is written and stored to the storage means. At least a first randomization process is underlying the encoding process and is a randomization process dedicated and assigned to the underlying storage means. The present disclosure further refers to a unit for operating a storage means, to a storage means and to a system for processing data. By having two randomization processes underlying the encoding process, a distinction can be made between a secrecy insuring and secrecy non-ensuring randomization processes.

Abstract: A method and apparatus for controlling access to memory is disclosed. In one implementation, a memory controller may receive a memory access request that may include a virtual memory address, a device identifier (ID) and a protected access indicator. Additionally, the memory controller can receive page table entries including a physical memory address based on the virtual memory address and a security attribute associated with the physical memory address. The memory controller may access a memory based on the physical memory address, the security attribute, the protected access indicator, and the device ID.

Abstract: A method for compressing data in a local cache of a web server is described. A local cache compression engine accesses values in the local cache and determines a cardinality of the values of the local cache. The local cache compression engine determines a compression rate of a compression algorithm based on the cardinality of the values of the local cache. The compression algorithm is applied to the cache based on the compression rate to generate a compressed local cache.

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

Abstract: A control system for a storage apparatus includes two input/output modules (IOMs), and two non-volatile memory (NVM) devices that are electrically connected to the IOMs, respectively, and that each store a firmware code. Each of the IOMs is configured to execute a firmware corresponding to the firmware code stored in the corresponding NVM device, and to enter an active mode or a passive mode after executing the firmware. The IOMs are configured such that when one IOM operating in the passive mode detects abnormal operation of the other IOM operating in the active mode, the one IOM sends, to the other IOM, the firmware code stored in the NVM device electrically connected to the one IOM, in order to update the firmware code in the NVM device electrically connected to the other IOM.

Abstract: A storage device includes a memory device including a plurality of zones, each of the plurality of zones having a plurality of memory blocks, a buffer memory device including a host buffer receiving write data to be stored in one of the plurality of zones, and a memory buffer temporarily storing the write data transmitted from the host buffer, a buffer controller configured to control the buffer memory device to transmit the write data to the memory device, and a write operation controller configured to control the memory device to store the write data in the one of the plurality of one zones. The write operation controller controls the memory device to obtain the previously stored data and a corrected write data and to store the previously stored data and the corrected write data in a second memory block group after the write operation controller detects an error in the write data.

Abstract: Techniques for submitting unaligned IO data to an alignment-required IO stack of a storage system. The techniques include determining that IO data specified by an IO command contains unaligned IO data, and generating an IOCB and a tunneling IOCB. The IOCB includes information pertaining to the tunneling IOCB and the tunneling IOCB includes information pertaining to a sector-unaligned buffer for storing the IO data. The tunneling IOCB satisfies a sector-alignment requirement of an IO stack. The techniques include, in response to submitting the IO command and the information included in the IOCB to the IO stack, determining that the tunneling IOCB satisfies the sector-alignment requirement of the IO stack; having satisfied the sector-alignment requirement, building a driver command based on the IO command and the information included in the tunneling IOCB; and, transferring, by executing the driver command, the unaligned IO data from the sector-unaligned buffer to a storage device.

Abstract: According to one embodiment, a memory system includes a first memory and a controller. The controller includes first and second decoders, first and second circuits, a register, and a switching circuit. The first and second decoders decode first and second commands respectively, which include first and second addresses respectively. The first and second circuits access the first memory using the first and second addresses respectively. A value stored in the register is changeable by a host. The switching circuit switches between the first and second circuits to access the first memory according to the value in the register.

Abstract: Rapid writing to and reading from even very large amounts of data, especially where the data evolves more slowly over time. For each of a sequence of commits of the data, the data is represented by identifying pages of the data that have changed since a prior commit in the sequence of commits. A sparce file is formulate for the commit, and contains each of identified pages, and for each identified page a mapping of the identified to a page address of the identified page in the address range. The sparce file is then stored as associated with the corresponding commit. Thus, an ordered sequence of sparce files can be created and layered on top of a base file that represents the entire page address range. The sparce files may be quite small as there may be relatively few pages (or perhaps even no pages) that changed since the prior commit in the sequence of commits. Reads occur by creating a sparce in-memory object, and checking for each page at each sparce.

Abstract: Wear on a zoned storage device can be reduced in some examples. One particular example can involve a system that can receive delete requests configured for erasing multiple files from a zone of a zoned storage device. In response to receiving the deleting requests, the system can update a log to indicate that the multiple files in the zone are to be erased. The system can determine, based on the log, that a predefined amount of data encompassing the multiple files in the zone is to be erased. The system can then transmit a command to the zoned storage device for causing the predefined amount of data in the zone to be erased. Erasing the data in this way may reduce write amplification and thereby increase the longevity of the zoned storage device.

Abstract: An apparatus comprises processing circuitry to issue memory access requests specifying a target address identifying a location to be accessed in a memory system; and a memory protection unit (MRU) comprising permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system. The memory protection table comprises memory protection entries each specifying access permissions for a corresponding address region of variable size within an address space, where the variable size can be a number of bytes other than a power of 2.