Patents by Inventor Aaron A. Budrevich
Aaron A. Budrevich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935887Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.Type: GrantFiled: March 28, 2019Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Ryan Keech, Nicholas Minutillo, Anand Murthy, Aaron Budrevich, Peter Wells
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Publication number: 20230420246Abstract: An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. A region including metals and semiconductor materials is between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopants is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region, and wherein the section of the source or drain region is at a distance of at most 5 nanometers (nm) from the region.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Ilya V. Karpov, Aaron A. Budrevich, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Dan S. Lavric
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Publication number: 20230420574Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Seung Hoon Sung, Ashish Agrawal, Jack T. Kavalieros, Rambert Nahm, Natalie Briggs, Susmita Ghose, Glenn Glass, Devin R. Merrill, Aaron A. Budrevich, Shruti Subramanian, Biswajeet Guha, William Hsu, Adedapo A. Oni, Rahul Ramamurthy, Anupama Bowonder, Hsin-Ying Tseng, Rajat K. Paul, Marko Radosavljevic
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Publication number: 20230343826Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Cory BOMBERGER, Anand MURTHY, Anupama BOWONDER, Aaron BUDREVICH, Tahir GHANI
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Patent number: 11735630Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.Type: GrantFiled: January 3, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Cory Bomberger, Anand Murthy, Anupama Bowonder, Aaron Budrevich, Tahir Ghani
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Patent number: 11264453Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.Type: GrantFiled: May 14, 2019Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Cory E. Weber, Aaron D. Lilak, Szuya S. Liao, Aaron A. Budrevich
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Patent number: 11222947Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.Type: GrantFiled: September 25, 2015Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Cory E. Weber, Aaron D. Lilak, Szuya S. Liao, Aaron A. Budrevich
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Patent number: 10896907Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.Type: GrantFiled: September 30, 2016Date of Patent: January 19, 2021Assignee: Intel CorporationInventors: Patrick H. Keys, Hei Kam, Rishabh Mehandru, Aaron A. Budrevich
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Methods for doping a sub-fin region of a semiconductor fin structure and devices containing the same
Patent number: 10896852Abstract: Methods for doping a subfin region of a semiconductor fin structure include forming a fin on a substrate; forming an oxide material on the substrate and a portion of the fin that corresponds to a sub-fin region of the fin; forming a hard mask on a top-fin region of the fin that is disposed above the sub-fin region; exposing a surface of the sub-fin region by removing the oxide material from a surface of the sub-fin region and leaving a layer of the oxide material on the substrate; depositing a dopant material on the hard mask, the surface of the subfin region, and the layer of the oxide material on the substrate; and removing the hard mask from the top-fin region to expose a surface of the top-fin region. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.Type: GrantFiled: September 17, 2015Date of Patent: January 19, 2021Assignee: Intel CorporationInventors: Scott B. Clendenning, Martin Mitan, Aaron A. Budrevich -
Patent number: 10847653Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.Type: GrantFiled: January 17, 2017Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Martin D. Giles, Annalisa Cappellani, Sanaz Gardner, Rafael Rios, Cory E. Weber, Aaron A. Budrevich
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Publication number: 20200312842Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Ryan KEECH, Nicholas MINUTILLO, Anand MURTHY, Aaron BUDREVICH, Peter WELLS
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Publication number: 20200219975Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.Type: ApplicationFiled: January 3, 2019Publication date: July 9, 2020Inventors: Cory BOMBERGER, Anand MURTHY, Anupama BOWONDER, Aaron BUDREVICH, Tahir GHANI
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METHODS FOR DOPING A SUB-FIN REGION OF A SEMICONDUCTOR FIN STRUCTURE AND DEVICES CONTAINING THE SAME
Publication number: 20200211901Abstract: Methods for doping a subfin region of a semiconductor fin structure include forming a fin on a substrate; forming an oxide material on the substrate and a portion of the fin that corresponds to a sub-fin region of the fin; forming a hard mask on a top-fin region of the fin that is disposed above the sub-fin region; exposing a surface of the sub-fin region by removing the oxide material from a surface of the sub-fin region and leaving a layer of the oxide material on the substrate; depositing a dopant material on the hard mask, the surface of the subfin region, and the layer of the oxide material on the substrate; and removing the hard mask from the top-fin region to expose a surface of the top-fin region.Type: ApplicationFiled: September 17, 2015Publication date: July 2, 2020Inventors: Scott B. CLENDENNING, Marvin MITAN, Aaron A. BUDREVICH -
Publication number: 20190267448Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Applicant: Intel CorporationInventors: Cory E. Weber, Aaron D. Lilak, Szuya S. Liao, Aaron A. Budrevich
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Publication number: 20190237466Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.Type: ApplicationFiled: September 30, 2016Publication date: August 1, 2019Inventors: Patrick H. KEYS, Hei KAM, Rishabh MEHANDRU, Aaron A. BUDREVICH
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Publication number: 20180254320Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.Type: ApplicationFiled: September 25, 2015Publication date: September 6, 2018Applicant: Intel CorporationInventors: Cory E. Weber, Aaron D. Lilak, Szuya S. Liao, Aaron A. Budrevich
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Patent number: 10008565Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: GrantFiled: June 16, 2017Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Publication number: 20170288019Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: Willy RACHMADY, Van H. LE, Ravi PILLARISETTY, Jessica S. KACHIAN, Marc C. FRENCH, Aaron A. BUDREVICH
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Patent number: 9691848Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: GrantFiled: October 25, 2016Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Publication number: 20170125591Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.Type: ApplicationFiled: January 17, 2017Publication date: May 4, 2017Inventors: Martin D. GILES, Annalisa CAPPELLANI, Sanaz KABEHIE, Rafael RIOS, Cory E. WEBER, Aaron A. BUDREVICH