Patents by Inventor Aaron Lilak

Aaron Lilak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210257492
    Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 19, 2021
    Applicant: Intel Corporation
    Inventors: Aaron Lilak, Patrick Keys, Sayed Hasan, Stephen Cea, Anupama Bowonder
  • Patent number: 11049861
    Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Morrow, Rishabh Mehandru, Donald W. Nelson, Stephen M. Cea
  • Publication number: 20210159312
    Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 27, 2021
    Applicant: Intel Corporation
    Inventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
  • Patent number: 10892326
    Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
  • Publication number: 20200411315
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Ehren MANNEBACH, Patrick MORROW, Anh PHAN, Willy RACHMADY, Hui Jae YOO
  • Publication number: 20200411660
    Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Kevin L. LIN, Tristan TRONIC
  • Publication number: 20200411644
    Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Aaron LILAK, Rishabh MEHANDRU, Willy RACHMADY, Harold KENNEL, Tahir GHANI
  • Publication number: 20200411651
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY
  • Publication number: 20200411365
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Ehren MANNEBACH, Patrick MORROW, Anh PHAN, Willy RACHMADY, Hui Jae YOO
  • Publication number: 20200411430
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Rishabh MEHANDRU
  • Publication number: 20200411511
    Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Aaron LILAK, Patrick MORROW, Anh PHAN, Ehren MANNEBACH, Jack T. KAVALIEROS
  • Publication number: 20200411639
    Abstract: A device is disclosed. The device includes a first gate conductor, a first source-drain region adjacent a first side of the first gate conductor and a second source-drain region adjacent a second side of the first gate conductor, a second gate conductor below the first gate conductor, a third source-drain region below the first source-drain region and adjacent a first side of the second gate conductor and a fourth source-drain region below the second source-drain region and adjacent a second side of the second gate conductor, a first air gap space between the first source-drain region and a first side of the first gate conductor and a second air gap space between the second source-drain region and the second side of the second gate conductor. A planar dielectric layer is formed above the first gate conductor.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Anh PHAN, Hui Jae YOO, Patrick MORROW, Cheng-Ying HUANG, Willy RACHMADY, Gilbert DEWEY
  • Publication number: 20200411433
    Abstract: Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.
    Type: Application
    Filed: February 22, 2018
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Aaron Lilak, Anh Phan, Gilbert Dewey, Willy Rachmady, Patrick Morrow
  • Publication number: 20200411526
    Abstract: A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Abhishek SHARMA, Willy RACHMADY, Van H. LE, Travis W. LAJOIE, Urusa ALAAN, Hui Jae YOO, Sean MA, Aaron LILAK
  • Patent number: 10861870
    Abstract: A semiconductor stacked device include a first plurality of device layers separated from one another by a first plurality of dielectric layers, a first electrically conductive via coupled to a contact portion of a device layer of the first plurality of the device layers, a second plurality of device layers separated from one another by a second plurality of dielectric layers, and a second electronically conductive via coupled to a contact portion of a device layer of the second plurality of the device layers. The first electronically conductive via extends to a frontside of the semiconductor stacked device and the second electrically conductive via extends to a backside of the semiconductor stacked device. The first plurality of device layers form a stair pattern in a first direction and the second plurality of device layers form a stair pattern in a second direction inverted from the first direction.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Morrow, Rishabh Mehandru
  • Publication number: 20200335501
    Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.
    Type: Application
    Filed: March 2, 2018
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Cheng-ying Huang, Willy Rachmady, Aaron Lilak
  • Publication number: 20200303191
    Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Anant JAHAGIRDAR, Chytra PAWASHE, Aaron LILAK, Myra MCDONNELL, Brennen MUELLER, Mauro KOBRINSKY
  • Publication number: 20200303238
    Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Rishabh MEHANDRU, Hui Jae YOO, Patrick MORROW, Kevin LIN
  • Publication number: 20200258894
    Abstract: A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.
    Type: Application
    Filed: February 11, 2019
    Publication date: August 13, 2020
    Inventors: Aaron LILAK, Patrick MORROW, Sayed HASAN
  • Publication number: 20200235013
    Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.
    Type: Application
    Filed: August 24, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Aaron Lilak, Sean Ma, Justin R. Weber, Rishabh Mehandru, Stephen M. Cea, Patrick Morrow, Patrick H. Keys