Patents by Inventor Abbas Jamshidi Roudbari

Abbas Jamshidi Roudbari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190087051
    Abstract: A self-capacitive touch sensor panel configured to have a portion of both the touch and display functionality integrated into a common layer is provided. The touch sensor panel includes a layer with circuit elements that can switchably operate as both touch circuitry and display circuitry such that during a touch mode of the device the circuit elements operate as touch circuitry and during a display mode of the device the circuit elements operate as display circuitry. The touch mode and display mode can be time multiplexed. By integrating the touch hardware and display hardware into common layers, savings in power, weight and thickness of the device can be realized.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Inventors: Weijun YAO, Wei Hsin YAO, Yingxuan LI, Bingrui YANG, Marduke YOUSEFPOR, Abbas JAMSHIDI-ROUDBARI, Ahmad AL-DAHLE
  • Publication number: 20190073976
    Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.
    Type: Application
    Filed: May 15, 2018
    Publication date: March 7, 2019
    Inventors: Shin-Hung Yeh, Abbas Jamshidi Roudbari, Ting-Kuo Chang
  • Publication number: 20190067407
    Abstract: A display may have display driver circuitry. Signal routing lines may supply multiplexed signals from the display driver circuitry to demultiplexer circuitry. The demultiplexer circuitry may provide corresponding demultiplexed signals to the pixels over signal routing lines. The demultiplexer circuitry may have demultiplexer circuit blocks such as 1:N demultiplexer circuit blocks. Each of the demultiplexer circuit blocks may have the same area and layout. The demultiplexer circuit blocks may run across the width of the display. A first portion of the demultiplexer circuit blocks may extend in a straight line parallel to an edge of the active area. A second portion of the demultiplexer circuit blocks may be arranged in a staircase pattern that angles away from the first portion of demultiplexer circuit blocks.
    Type: Application
    Filed: May 21, 2018
    Publication date: February 28, 2019
    Inventors: Cheng-Ho Yu, Abbas Jamshidi Roudbari, Shin-Hung Yeh, Sungki Lee, Ting-Kuo Chang, Yu Cheng Chen
  • Publication number: 20190057646
    Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.
    Type: Application
    Filed: June 1, 2018
    Publication date: February 21, 2019
    Inventors: Chin-Wei Lin, Shyuan Yang, Chuang Qian, Abbas Jamshidi Roudbari, Ting-Kuo Chang
  • Patent number: 10209813
    Abstract: A self-capacitive touch sensor panel configured to have a portion of both the touch and display functionality integrated into a common layer is provided. The touch sensor panel includes a layer with circuit elements that can switchably operate as both touch circuitry and display circuitry such that during a touch mode of the device the circuit elements operate as touch circuitry and during a display mode of the device the circuit elements operate as display circuitry. The touch mode and display mode can be time multiplexed. By integrating the touch hardware and display hardware into common layers, savings in power, weight and thickness of the device can be realized.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 19, 2019
    Assignee: APPLE INC.
    Inventors: Weijun Yao, Wei Hsin Yao, Yingxuan Li, Bingrui Yang, Marduke Yousefpor, Abbas Jamshidi-Roudbari, Ahmad Al-Dahle
  • Publication number: 20190043418
    Abstract: A display may have rows and columns of pixels that form an active area for displaying images. A display driver integrated circuit may provide multiplexed data signals to demultiplexer circuitry in the display. The demultiplexer circuitry may demultiplex the data signals and provide the demultiplexed data signals to the pixels on data lines. Gate lines may control the loading of the data signals into the pixels. The display may have a length dimension and a width dimension that is shorter than the length dimension. The data lines may extend parallel to the width dimension and the gate lines may extend parallel to the length dimension such that there are more data lines than gate lines in the display. A notch that is free of pixels may extend into the active area. Data lines extending parallel to the width dimension of the display may be routed around the notch.
    Type: Application
    Filed: May 9, 2018
    Publication date: February 7, 2019
    Inventors: Warren S. Rieutort-Louis, Shyuan Yang, Tsung-Ting Tsai, Cheng-Ho Yu, Jae Won Choi, Bhadrinarayana Lalgudi Visweswaran, Abbas Jamshidi Roudbari, Ting-Kuo Chang
  • Publication number: 20180366065
    Abstract: Aspects of the subject technology relate to display circuitry. The display circuitry includes gate-in-panel (GIP) control circuitry on opposing sides of a display pixel array. The GIP control circuitry can include scan drivers for each pixel row on both sides of that pixel row, the scan drivers on either side configured for enablement or disablement for single-sided reduced-power operations. The GIP control circuitry can include a single scan driver and a single emission controller for each pixel row, in which the scan driver and emission controller for each row are disposed on opposing sides of the row. The scan drivers for a first subset of the pixel rows can be interleaved with the emission controllers for a different subset of the pixel rows.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 20, 2018
    Inventors: Shyuan YANG, Abbas JAMSHIDI ROUDBARI, Ting-Kuo CHANG, Tsung-Ting TSAI, Warren S. RIEUTORT-LOUIS
  • Publication number: 20180366081
    Abstract: Electronic devices, storage medium containing instructions, and methods pertain to cancelling noise that results from application of clocks/clock drivers of a display. The electronic display may inject counter noise into the cathode. For example, the counter noise may be injected via a sensing layer, via unused clocks, and/or via a power rail of the display.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Mohammad Ali Jangda, Marc Joseph DeVincentis, Abbas Jamshidi-Roudbari, Warren S. Rieutort-Louis
  • Patent number: 10109240
    Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: October 23, 2018
    Assignee: Apple Inc.
    Inventors: Shih Chang Chang, Keitaro Yamashita, Shin-Hung Yeh, Ting-Kuo Chang, Abbas Jamshidi Roudbari, Chin-Wei Lin
  • Patent number: 10101853
    Abstract: Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: October 16, 2018
    Assignee: Apple Inc.
    Inventors: Yu Cheng Chen, Keitaro Yamashita, Abbas Jamshidi Roudbari, Hirokazu Yamagata, Ting-Kuo Chang
  • Patent number: 10078405
    Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The gate driver circuitry may include gate drivers connected in a chain. A given one of the gate drivers may include a set-reset latch. The set-reset latch may have a set input and a reset input. A logic gating circuit such as a logic NOR gate may have an output directly connected to the set input. The NOR gate may have a first input coupled to an output of a preceding gate driver in the chain and a second input coupled to an output of a succeeding gate driver. The reset input may be coupled to the output of the preceding gate driver. Gate line output signals may be simultaneously asserted for each of the drivers without generating unstable scenarios where logic high signals are provided to the set and reset inputs.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: September 18, 2018
    Assignee: Apple Inc.
    Inventors: Abbas Jamshidi Roudbari, Keitaro Yamashita
  • Patent number: 10048788
    Abstract: Improvement of visual uniformity of an integrated touch screen display is provided. A touch screen can include common electrodes separated by gaps in a Vcom layer. To improve visual non-uniformity in the display resulting from the gaps, a first set of semi-transparent dummy features (primary-dummy features) can be formed on a second layer at the locations of the gaps, and a second set of dummy features (supplementary-dummy features) can also be formed on the second layer or another layer to mitigate low spatial resolution of the primary-dummy features and/or non-uniform spacing of the primary-dummy features. In some examples, holes or slits can be formed in the Vcom layer at areas of the supplementary-dummy features to further improve visual uniformity.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 14, 2018
    Assignee: Apple Inc.
    Inventors: Yu Cheng Chen, Abbas Jamshidi-Roudbari, Hiroshi Osawa, Shang-Chih Lin, Shih-Chang Chang, Shin-Hung Yeh, Ting-Kuo Chang, Majid Gharghi, Keitaro Yamashita
  • Patent number: 10042409
    Abstract: Methods and devices useful in discharging an aberrant charge on a touch sensitive display of an electronic device are provided. By way of example, a an electronic device includes a power management and control circuitry configured to receive a first voltage signal and a second voltage signal from a display subsystem of a display of the electronic device, receive a third voltage signal from a touch subsystem of the display, provide a power signal to the display subsystem to activate the display subsystem when the display is determined to be in a temporarily inactive state. Providing the power signal to the display subsystem comprises discharging an aberrant charge based on the third voltage signal.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 7, 2018
    Assignee: Apple Inc.
    Inventors: Keitaro Yamashita, Majid Gharghi, Ting-Kuo Chang, Abbas Jamshidi Roudbari
  • Patent number: 10019090
    Abstract: A display may have an array of pixels. A transparent conductive layer may serve as a common voltage electrode layer and may distribute a common voltage to each of the pixels. Metal layers may be used to form routing structures. One of the metal layers may be patterned to form gate lines that distribute control signals to thin-film transistors in the pixels. Touch sensor circuitry may be coupled to horizontal and vertical capacitive touch sensor electrodes formed from the transparent conductive layer. A touch sensor signal border routing path in an inactive area of the display may have openings that run parallel to the gate lines and that each overlap one of the gate lines to reduce capacitive coupling between the gate lines and the touch sensor signal border routing path.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 10, 2018
    Assignee: Apple Inc.
    Inventors: Majid Gharghi, Sungki Lee, Abbas Jamshidi Roudbari, Shin-Hung Yeh, Ting-Kuo Chang, Yu Cheng Chen
  • Patent number: 9965063
    Abstract: A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. Each display pixel in the TFT layer may include first and second TFTs coupled in series between a data line and a storage capacitor. The first TFT may have a gate that is coupled to a gate line. The second TFT may have a gate that is coupled to a control line that is different than the gate line. A global enable signal may be provided on the control line, where the enable signal is asserted during display intervals and is deasserted during touch intervals. The second TFT may be formed using a top-gate TFT or a bottom-gate TFT arrangement.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: May 8, 2018
    Assignee: Apple Inc.
    Inventors: Abbas Jamshidi Roudbari, Shih-Chang Chang, Ting-Kuo Chang, Cheng-Ho Yu
  • Publication number: 20180088728
    Abstract: This relates to a force-sensitive touch screen including a metallization layer for force sensing. In some examples, the force-sensing metallization layer can be deposited between a color filter layer and a thin film transistor (TFT) layer (including an array of TFTs) of the touch screen. In some examples, the metallization layer can be electrically coupled to a patterned conductive layer. Together, a force-sensing metallization trace of the metallization layer and a patterned conductor of the patterned conductive layer can act as a force sensor. Additionally or alternatively, the device can include a force-sensing metallization layer and a conductive layer (patterned or not) located beneath the TFT layer (i.e., rather than between a color filter layer and the TFT layer).
    Type: Application
    Filed: September 14, 2017
    Publication date: March 29, 2018
    Inventors: Joshua G. WURZEL, Abbas JAMSHIDI-ROUDBARI, Ting-Kuo CHANG
  • Publication number: 20180075809
    Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.
    Type: Application
    Filed: January 10, 2017
    Publication date: March 15, 2018
    Inventors: Shih Chang Chang, Keitaro Yamashita, Shin-Hung Yeh, Ting-Kuo Chang, Abbas Jamshidi Roudbari, Chin-Wei Lin
  • Publication number: 20180075808
    Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be enabled to emit light in each frame. In the partial scanning mode, only a subset of the rows of the display may be enabled to emit light in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. To ensure uniform transistor stress across the display, the scanning driver for the display may scan the disabled rows in the partial scanning mode even though the rows will not be used to emit light.
    Type: Application
    Filed: December 19, 2016
    Publication date: March 15, 2018
    Inventors: Keitaro Yamashita, Abbas Jamshidi Roudbari, Shin-Hung Yeh, Tsung-Ting Tsai, Shih-Chang Chang, Ting-Kuo Chang, Ki Yeol Byun, Warren S. Rieutort-Louis
  • Publication number: 20170351379
    Abstract: Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.
    Type: Application
    Filed: September 8, 2016
    Publication date: December 7, 2017
    Inventors: Yu Cheng Chen, Keitaro Yamashita, Abbas Jamshidi Roudbari, Hirokazu Yamagata, Ting-Kuo Chang
  • Publication number: 20170269744
    Abstract: A display may have an array of pixels. A transparent conductive layer may serve as a common voltage electrode layer and may distribute a common voltage to each of the pixels. Metal layers may be used to form routing structures. One of the metal layers may be patterned to form gate lines that distribute control signals to thin-film transistors in the pixels. Touch sensor circuitry may be coupled to horizontal and vertical capacitive touch sensor electrodes formed from the transparent conductive layer. A touch sensor signal border routing path in an inactive area of the display may have openings that run parallel to the gate lines and that each overlap one of the gate lines to reduce capacitive coupling between the gate lines and the touch sensor signal border routing path.
    Type: Application
    Filed: August 16, 2016
    Publication date: September 21, 2017
    Inventors: Majid Gharghi, Sungki Lee, Abbas Jamshidi Roudbari, Shin-Hung Yeh, Ting-Kuo Chang, Yu Cheng Chen