Patents by Inventor Abd. Razak Bin Chichik

Abd. Razak Bin Chichik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9269601
    Abstract: A method of manufacturing a semiconductor element is provided. The method includes the following steps. A carrier and a mold are provided. A first patterned conductive layer including a plurality of traces is formed on the carrier. A second patterned conductive layer is formed on the first patterned conductive layer. The carrier is disposed with the mold to form at least one mold cavity. The mold cavity is infused with a molding material. The molding material fills the mold cavity to encapsulate the first and second patterned conductive layers. The carrier is removed by etching to expose the plurality of traces embedded in the molding material without affecting the width of the traces.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: February 23, 2016
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Chew Hwee-Seng Jimmy, Ong Chee Kian, Abd. Razak Bin Chichik
  • Publication number: 20100264526
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Application
    Filed: June 29, 2010
    Publication date: October 21, 2010
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Chew Hwee-Seng Jimmy, Ong Chee Kian, Abd. Razak Bin Chichik
  • Patent number: 7795071
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: September 14, 2010
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Chew Hwee-Seng Jimmy, Ong Chee Kian, Abd. Razak Bin Chichik
  • Publication number: 20090291530
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 26, 2009
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Chew Hwee-Seng JIMMY, Ong Chee Kian, Abd. Razak Bin Chichik
  • Publication number: 20090102043
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Application
    Filed: November 26, 2008
    Publication date: April 23, 2009
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Chew Hwee-Seng Jimmy, Ong Chee Kian, Abd. Razak Bin Chichik
  • Publication number: 20080150107
    Abstract: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.
    Type: Application
    Filed: March 6, 2008
    Publication date: June 26, 2008
    Applicant: ADVANPACK SOLUTION PTES LTD
    Inventors: Teck Tiong TAN, Hwee Seng Jimmy CHEW, Kok Yeow Eddy LIM, Abd. Razak Bin CHICHIK, Kee Kwang LAU, Chuan Wei WONG
  • Publication number: 20080150561
    Abstract: A device and a method for testing a semiconductor element, and manufacturing method thereof are provided. The apparatus includes a substrate and a conductive macromolecular elastic structure. The conductive macromolecular elastic structure is disposed on the substrate and defines a receiving space for receiving a conductive bump of the semiconductor element in order to test the semiconductor element.
    Type: Application
    Filed: December 26, 2007
    Publication date: June 26, 2008
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Chew Hwee-Seng Jimmy, Ong Chee Kian, Wang Zhiping, Ma Zhaohui, Abd. Razak Bin Chichik