Abstract: Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus includes a receptacle to receive a plug of a first device and a second device; a transceiver circuit coupled to the receptacle; and a controller circuit to: switch between a first mode for a first class of data transfers and a second mode for a second class of data transfers, wherein the first class preempts the second class of data transfers, schedule a data transfer with the transceiver circuit for a first endpoint of the first device at a first service interval of a bus interval when in the first mode, and schedule a data transfer with the transceiver circuit for a second, different endpoint of the second device at a second service interval that is smaller than the first service interval when in the first mode.

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may be operable to provide output to a unidirectional data path for carrying a packetized data stream. The second circuitry may be operable to provide output to, and obtain input from, a bidirectional control path for carrying a packetized control stream. The packetized data stream may comprise pixel data traffic and frame-synchronous metadata traffic, and the packetized control stream may comprise frame-asynchronous metadata traffic and control traffic.

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract: Techniques for latency improvement are described herein. The techniques may include an apparatus having a receiver configured to receive transfers over a bus. The transfers include a periodic transfer at a predefined interval, wherein the periodic transfer is associated with a guaranteed bandwidth over the bus. The transfers may also include an asynchronous transfer at any time within the predefined interval. The apparatus may also include logic configured to implement a modified periodic transfer at an interval that is less than the predefined interval, and a modified asynchronous transfer comprising a priority status above the asynchronous transfer.

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract: Systems and methods that provide that provide the sharing of capabilities over a communicative link, such as a network, is disclosed. The capabilities may be shared seamlessly between electronic devices by using preexisting device drivers.

Abstract: A method for managing data between a virtual machine a bus controller includes transmitting an input output (IO) request from the virtual machine to a service virtual machine that owns the bus controller. According to an alternate embodiment, managing data between a virtual machine and a bus controller includes trapping a register access made by the virtual machine. A schedule is generated to be implemented by the bus controller. Status is returned to the virtual machine via a virtual host controller. Other embodiments are described and claimed.

Abstract: Methods and systems may include an apparatus having a power line interface and a controller with management logic. The management logic can manage the power delivery policies of devices connected to the power line interface based on changes in the power delivery capability of the apparatus.

Abstract: A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.

Abstract: A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.

Abstract: Methods and systems may include an apparatus having a power line interface and a controller with management logic. The management logic can manage the power delivery policies of devices connected to the power line interface based on changes in the power delivery capability of the apparatus.

Abstract: A method for managing data between a virtual machine a bus controller includes transmitting an input output (IO) request from the virtual machine to a service virtual machine that owns the bus controller. According to an alternate embodiment, managing data between a virtual machine and a bus controller includes trapping a register access made by the virtual machine. A schedule is generated to be implemented by the bus controller. Status is returned to the virtual machine via a virtual host controller. Other embodiments are described and claimed.

Abstract: A method for performing virtualization, includes managing data between a virtual machine and a bus controller by transmitting an input output (IO) request from the virtual machine to a service virtual machine that owns the bus controller. According to an alternate embodiment, the method for performing virtualization includes managing isochronous data between a virtual machine and a bus controller. Other embodiments are described and claimed.

Abstract: Embodiments include systems and methods for management of RPIPES in a Wireless Universal Serial Bus (WUSB) environment comprising at least one WUSB device. RPIPE management computer code is executed to perform RPIPE management functions including monitoring RPIPE memory usage, and storing transfer requests in a queue in memory of the host machine while awaiting availability of Host Wire Adapter (HWA) memory.

Abstract: An apparatus and method for remote USB host controlling are described herein.