Patents by Inventor Abdurrahman Sezginer

Abdurrahman Sezginer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8069423
    Abstract: Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: November 29, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Justin Ghan, Abdurrahman Sezginer
  • Publication number: 20110113393
    Abstract: Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 12, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Abdurrahman SEZGINER
  • Patent number: 7913197
    Abstract: According to various embodiments of the invention systems and methods for multiple pattern lithography, wherein a target layout pattern that is not capable of being printed in one lithography step is decomposed into multiple patterns that are printable in one lithography operation and, when appropriate, a continuous junction is utilized for where patterns overlap. In a further embodiment, where a continuous junction is not utilized, a splice is utilized at overlap locations. In yet another embodiment, where splices are utilized for overlap locations, identifying where critical nets are located in the target layout pattern, determining how close a component of the critical net is to a splice, and changing the target layout pattern as to avoid the condition of a component of the critical net being in proximity to a splice. In another embodiment of the invention, where splices are utilized at overlap locations, placing a landing pad of contacts or vias at the same location as the splice.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: March 22, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michiel Victor Paul Kruger, Bayram Yenikaya, Anwei Liu, Abdurrahman Sezginer, Wolf Staud
  • Publication number: 20110014786
    Abstract: Disclosed are a method, apparatus, and program product for routing an electronic design using double patenting that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patenting, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.
    Type: Application
    Filed: October 20, 2009
    Publication date: January 20, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Abdurrahman Sezginer, David Cooke Noice, Jason Sweis, Vassilios Gerousis, Sozen Yao
  • Patent number: 7856613
    Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: December 21, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Milind Weling, Judy Huckabay, Abdurrahman Sezginer
  • Patent number: 7849423
    Abstract: A photomask dataset corresponding to a target-pattern is verified by simulating a resist-pattern that will be formed in a resist layer by a lithography process, simulating an etched-pattern that will be etched in a layer by a plasma process wherein said simulation comprises calculating a flux of particles impacting a feature, and determining whether the etched-pattern substantially conforms to the target-pattern.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 7, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bayram Yenikaya, Devendra Joshi, Paul A. Fornari, Jesus O. Carrero, Abdurrahman Sezginer
  • Publication number: 20100186000
    Abstract: An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 22, 2010
    Inventors: ABDURRAHMAN SEZGINER, Bayram Yenikaya, Hsu-Ting Huang
  • Patent number: 7743359
    Abstract: An apparatus and method of synthesizing a photolithographic data set includes using a first computational model to calculate a first figure-of-merit for the photolithographic data set; changing a first part of the photolithographic data set to increase the first figure-of-merit; and then using a second computational model to calculate a second figure-of-merit of the photolithographic data set; and changing a second part of the photolithographic data set to increase the second figure-of-merit. The second computational model enables figure-of-merit calculations to be executed at a significantly faster execution rate than the first computational model.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: June 22, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Roy Prasad, Chi-Song Horng, Hsu-Ting Huang
  • Patent number: 7743358
    Abstract: An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: June 22, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Bayram Yenikaya, Hsu-Ting Huang
  • Publication number: 20100037200
    Abstract: Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.
    Type: Application
    Filed: August 11, 2008
    Publication date: February 11, 2010
    Inventors: Justin Ghan, Abdurrahman Sezginer
  • Publication number: 20090307649
    Abstract: The present invention provides a method for compensating, infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 10, 2009
    Inventors: Dipankar Pramanik, Michiel Victor Paul Kruger, Roy V. Prasad, Abdurrahman Sezginer
  • Patent number: 7600212
    Abstract: A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to a target polygon of the set of target polygons, the curve having a set of etch-target points; (c) moving the etch target points according to a model of an etch process to produce a set of lithography-target points; and (d) synthesizing a photomask data set based on a model of a lithography process and the set of lithography-target points.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: October 6, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Franz X. Zach, Jesus Carrero, Bayram Yenikaya, Gokhan Percin, Xuelong Cao, Abdurrahman Sezginer
  • Patent number: 7588868
    Abstract: First and second exposures of a mask onto a wafer are performed such that the exposure field of the second exposure partially overlaps the exposure field of the first exposure. A characteristic of a set of features is determined, and a value of a parameter of an optical proximity correction model is determined. An alignment feature can be used to align a measurement tool. In yet another embodiment, pupil intensity distribution of an imaging system is measured by exposing an image field of a radiation detector with a bright feature, positioning the detector at a distance away from the image plane, and exposing the image field of the detector with a bright feature, resulting in a cumulative exposure of the image field of the detector from the two exposures. A characteristic of a spatial pattern in the cumulative exposure of the image field of the detector is then determined.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: September 15, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Franz X. Zach, Abdurrahman Sezginer, Gokhan Percin
  • Patent number: 7568174
    Abstract: A technique for determining, without having to perform optical proximity correction, when the result of optical proximity correction will fail to meet the design requirements for printability. A disclosed embodiment has application to a process for producing a photomask for use in the printing of a pattern on a wafer by exposure with optical radiation to optically image the photomask on the wafer. A method is set forth for checking the printability of a target layout proposed for defining the photomask, including the following steps: deriving a system of inequalities that expresses a set of design requirements with respect to the target layout; and checking the printability of the target layout by determining whether the system of inequalities is feasible.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: July 28, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Bayram Yenikaya
  • Publication number: 20090146322
    Abstract: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Inventors: MILIND WELING, Abdurrahman Sezginer
  • Patent number: 7519940
    Abstract: An apparatus and method of compensating for lens imperfections in a projection lithography tool, includes extracting from a diffraction image created by the projection lithography tool a lens transmittance function, and then using the extracted lens transmittance function as a compensator in the lithography projection tool. Another preferred apparatus and method of synthesizing a photomask pattern includes obtaining a phase and an amplitude of a transmittance function of an imaging system; forming a computational model of patterning that includes the transmittance function of the imaging system; and then synthesizing a mask pattern from a given target pattern, by minimizing differences between the target pattern and another pattern that the computational model predicts the synthesized mask pattern will form on a wafer.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: April 14, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hsu-Ting Huang, Abdurrahman Sezginer
  • Patent number: 7506300
    Abstract: A method of modifying polygons in a data set mask-less or mask based optical projection lithography includes: 1) mapping the data set to a figure-of-demerit; 2) moving individual polygon edges to decrease the figure-of-demerit; and 3) disrupting the set of polygons to enable a further decrease in the figure-of-demerit, wherein disrupting polygons includes any of the following polygon disruptions: breaking up, merging, or deleting polygons.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: March 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Roy Prasad
  • Patent number: 7480891
    Abstract: An apparatus and method for improving image quality in a photolithographic process includes calculating a figure-of-demerit for a photolithographic mask function and then adjusting said photolithographic mask function to reduce the figure of demerit.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: January 20, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Abdurrahman Sezginer
  • Patent number: 7471392
    Abstract: An optical measurement system for evaluating a sample has a motor-driven rotating mechanism coupled to an azimuthally rotatable measurement head, allowing the optics to rotate with respect to the sample. A polarimetric scatterometer, having optics directing a polarized illumination beam at non-normal incidence onto a periodic structure on a sample, can measure optical properties of the periodic structure. An E-O modulator in the illumination path can modulate the polarization. The head optics collect light reflected from the periodic structure and feed that light to a spectrometer for measurement. A beamsplitter in the collection path can ensure both S and P polarization from the sample are separately measured. The measurement head can be mounted for rotation of the plane of incidence to different azimuthal directions relative to the periodic structures. The instrument can be integrated within a wafer process tool in which wafers may be provided at arbitrary orientation.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: December 30, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Adam E. Norton, Abdurrahman Sezginer, Fred E. Stanke
  • Patent number: 7444615
    Abstract: A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: October 28, 2008
    Assignee: Invarium, Inc.
    Inventors: Gokhan Percin, Ram S. Ramanujam, Franz X. Zach, Abdurrahman Sezginer, Chi-Song Horng, Roy Prasad