Abstract: A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.

Abstract: A method and system providing a multi-memristive synaptic element for a cognitive computing system. The multi-memristive synaptic element comprises an array of memristive devices. The method comprises arbitrating a synaptic weight allocation, a related synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, updating said synaptic weight variable by a delta amount, and assigning said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices requiring to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element.

Abstract: The device provides a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors, of the resistive memory device, wherein the resistive memory device provides a first crossbar array of the components, wherein the components are memristive 2D components addressable by word-lines and bit-lines, and a peripheral circuit connected to the word-lines and bit-lines and adapted for encoding operations by activating the word-lines and bit-lines sequentially in a predefined manner.

Abstract: Embodiments of the invention are directed to a method to modify material properties of a functional material of a nanoscale device post-fabrication. The method includes performing one or more conditioning steps. The conditioning steps include applying electrical conditioning signals of predefined form to the nanoscale device, thereby performing an in-situ heating of the functional material and inducing thermally a displacement of atoms, molecules or ions of the functional material of the nanoscale device. Embodiments of the invention further concerns a related electronic device.

Abstract: A resistive memory cell is connected in circuitry which has a first input terminal for applying neuron input signals including a read portion and a write portion. The circuitry includes a read circuit producing a read signal dependent on resistance of the memory cell, and an output terminal providing a neuron output signal, dependent on the read signal in a first state of the memory cell. The circuitry also includes a storage circuit storing a measurement signal dependent on the read signal, and a switch set operable to supply the read signal to the storage circuit during application of the read portion of each neuron input signal to the memory cell, and, after application of the read portion, to apply the measurement signal in the apparatus to enable resetting of the memory cell to a second state.

Abstract: A method, computer system, and computer program product of performing a matrix convolution on a multidimensional input matrix for obtaining a multidimensional output matrix. The matrix convolution may include a set of dot product operations for obtaining all elements of the output matrix. Each dot product operation of the set of dot product operations may include an input submatrix of the input matrix and at least one convolution matrix. The method may include providing a memristive crossbar array configured to perform a vector matrix multiplication. A subset of the set of dot product operations may be computed by storing the convolution matrices of the subset of dot product operations in the crossbar array and inputting to the crossbar array one input vector comprising all distinct elements of the input submatrices of the subset.

Abstract: A computer device, a non-transitory computer storage medium, and a computer-implemented method of pattern recognition utilizing an elastic clustering algorithm. A sequence of input datapoints are assigned to a particular cluster of K clusters based on a distance from a centroid k representing a center of the particular cluster. The centroid kin each of the K clusters is shifted from a first position to a second position closer than the first position from the sequence of input datapoints. A location of the centroid k in each of the K clusters is relaxed from the second position toward an equilibrium point in the particular cluster of the K clusters. The relaxing of the location of the centroid k occurs according to an elasticity pull factor based on a distance between the centroid k of the particular cluster at a time t.

Abstract: Methods and apparatus are provided for memorizing data signals in a spiking neural network. For each data signal, such a method includes supplying metadata relating to the data signal to a machine learning model trained to generate an output signal, indicating a relevance class for a data signal, from input metadata for that data signal. The method includes iteratively supplying the data signal to a sub-assembly of neurons, interconnected via synaptic weights, of a spiking neural network and training the synaptic weights to memorize the data signal in the sub-assembly. The method further comprises assigning neurons of the network to the sub-assembly in dependence on the output signal of the model such that more relevant data signals are memorized by larger sub-assemblies. The data signal memorized by a sub-assembly can be subsequently recalled by activating neurons of that sub-assembly.

Abstract: The present disclosure relates to a method for executing a computation task composed of at least one set of operations where subsets of pipelineable operations of the set of operations are determined in accordance with a pipelining scheme. A single routine may be created for enabling execution of the determined subsets of operations by a hardware accelerator. The routine has, as arguments, a value indicative of input data and values of configuration parameters of the computation task, where a call of the routine causes a scheduling of the subsets of operations on the hardware accelerator in accordance with the values of the configuration parameters. Upon receiving input data of the computation task, the routine may be called to cause the hardware accelerator to perform by the computation task in accordance with the scheduling.

Abstract: A device performs a matrix-vector multiplication of a matrix with a vector. The device includes a crossbar array having row lines, column lines and junctions arranged between the row lines and the column lines. Each junction includes a programmable resistive element and an access element for accessing the programmable resistive element. The device further includes a signal generator configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication. The device further includes a readout circuit and control circuitry configured to control the signal generator and the readout circuit. The readout circuit is configured to apply read voltages having a positive voltage sign and negative read voltages having a negative voltage sign to the row lines of the crossbar array. The readout circuit is further configured to read out column currents of the plurality of column lines of the crossbar array.

Abstract: The present disclosure relates to an electronic system for computing items of an outer product matrix, for each item of at least part of the items of the matrix. The system is configured to receive a pair of real numbers of two vectors, the pair corresponding to said item. The system is further configured to compute a stochastic representation of the real numbers resulting in two sets of bits, the set of bits comprising a subset of bits representing the real number and a sign bit indicative of the sign of the real number. The system is further configured to perform a sequence of digital operations using the two sets of bits to provide a representation of said item.

Abstract: A sensor device comprising a computational memory and electronic circuitry. The sensor device is configured to receive an input signal, to compress the input signal into a compressed signal and to compute a reconstructed signal from the compressed signal. The electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal. The computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm. A related method and a related design structure may be provided.

Abstract: A system for hyper-dimensional computing for inference tasks may be provided. The device comprises an item memory for storing hyper-dimensional item vectors, a query transformation unit connected to the item memory, the query transformation unit being adapted for forming a hyper-dimensional query vector from a query input and hyper-dimensional base vectors stored in the item memory, and an associative memory adapted for storing a plurality of hyper-dimensional profile vectors and for determining a distance between the hyper-dimensional query vector and the plurality of hyper-dimensional profile vectors, wherein the item memory and the associative memory are adapted for in-memory computing using memristive devices.

Abstract: A device for hyper-dimensional computing may be provided. The device comprises a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors, of the resistive memory device, wherein the resistive memory device comprises a first crossbar array of the components, wherein the components are memristive 2D components addressable by word-lines and bit-lines, and a peripheral circuit connected to the word-lines and bit-lines and adapted for encoding operations by activating the word-lines and bit-lines sequentially in a predefined manner.

Abstract: The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.

Abstract: The present disclosure relates to a method for implementing processing elements in a chip card such that the processing elements can communicate data between each other in order to perform a computation task, wherein the data communication requires each processing element to have a respective number of connections to other processing elements. The method comprises: providing a complete graph with an even number of nodes that is higher than the maximum of the numbers of connections by one or two. If the number of processing elements is higher that the number of nodes of the graph, the graph may be duplicated and the duplicated graphs may be combined into a combined graph. A methodology for placing and connecting the processing elements may be determined in accordance with the structure of nodes of a resulting graph, the resulting graph being the complete graph or the combined graph.

Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n?1 and (p+n+m)=N where m?0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.

Abstract: The present disclosure relates to a method for implementing processing elements in a chip card such that the processing elements can communicate data between each other in order to perform a computation task, wherein the data communication requires each processing element to have a respective number of connections to other processing elements. The method comprises: providing a complete graph with an even number of nodes that is higher than the maximum of the numbers of connections by one or two. If the number of processing elements is higher that the number of nodes of the graph, the graph may be duplicated and the duplicated graphs may be combined into a combined graph. A methodology for placing and connecting the processing elements may be determined in accordance with the structure of nodes of a resulting graph, the resulting graph being the complete graph or the combined graph.