Abstract: A substrate processing chamber comprising a chamber wall enclosing a process zone having an exhaust port, a substrate support to support a substrate in the process zone, a gas distributor for providing a deposition gas to the process zone, a solid state light source capable of irradiating substantially the entire surface of the substrate with light, and a gas energizer for energizing the deposition gas.

Abstract: The present invention relates to combinations of materials and fabrication techniques which are useful in the fabrication of filled, metal-comprising gates for use in planar and 3D Field Effect Transistor (FET) structures. The FET structures described are of the kind needed for improved performance in semiconductor device structures produced at manufacturing nodes which implement semiconductor feature sizes in the 15 nm range or lower.

Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.

Abstract: The control of gate widths is improved for system-on-a-chip (SoC) devices which require multiple gate dielectric “gate” thicknesses, e.g., for analog and digital processing on the same chip. A hard mask is formed to protect a thick gate while the thin gate region is etched to remove oxide (sometimes referred to as a preclean step). The patterned substrate is then processed to selectively deposit a second thickness of gate material. The thin gate may be silicon oxide and the physical thickness of the thin gate may be less than that of the thick gate. In a preferred embodiment, the substrate is not exposed to air or atmosphere after the hardmask is removed.

Abstract: A three-dimensional structure disposed on a substrate is processed so as to alter the etch rate of material disposed on at least one surface of the structure. In some embodiments, a conformal deposition of material is performed on the three-dimensional structure. Subsequently, an ion implant is performed on at least one surface of the three-dimensional structure. This ion implant serves to alter the etch rate of the material deposited on that structure. In some embodiments, the ion implant increases the etch rate of the material. In other embodiments, the ion implant decreases the etch rate. In some embodiments, ion implants are performed on more than one surface, such that the material on at least one surface is etched more quickly and material on at least one other surface is etched more slowly.

Abstract: Embodiments of the present invention provide a lamination module and procedure for cooling the edges of a partially formed thin film solar module to substantially the same temperature as the central region of the module just prior to compressing and bonding the layers of the heated module. The lamination module may include a cooling module having a plurality of nozzles configured to apply a curtain of cooling fluid to leading and trailing edges of the partially formed solar module after heating the module and just prior to compressing the module. The nozzles may further be configured to apply a curtain of cooling fluid to side edges of the partially formed solar cell module as it passes through the cooling module. As a result, the chance of bubble formation within the bonding material in the edge regions of the completed solar cell module is significantly lowered with respect to conventional lamination processes.

Abstract: Methods for forming a thin film solar cell are provided. In one aspect, a thin film solar cell is formed by providing a back contact comprising a reflective material and an interface metal, applying a solder paste slurry that include a paste flux and metal particles to the interface metal and soldering at least one buss wire to back contact.

Abstract: Embodiments of the present invention generally relate to methods for cleaning a substrate prior to a deposition process. The methods generally include multiple cleaning solutions for removing contaminants from a surface of a substrate. The multiple solutions generally have different compositions, and each of the solutions contain one or more additives selected to remove a variety of contaminants. Mechanical agitation may also be utilized to remove contaminants from the surface of a substrate. After cleaning a substrate, a material may be deposited on the substrate surface.

Abstract: A series stack including a first and a second MVSD transistor is coupled between a positive power supply and a pad. The series stack has a central node. A p-driver including a first and a second P-type transistor is coupled in series with a source of the first p-type transistor coupled to a positive power supply. The drain of the second p-type transistor is coupled to the central node.

Abstract: A circuit device that includes a gate overlying an area of a semiconductor substrate, a well formed in the substrate proximate a first edge of the gate and doped with a first concentration of a first dopant, a channel region doped with a first concentration of a second dopant underlying a portion of the gate adjacent the well, a non-conducting region formed in the first portion of the well, and a contact to the second portion of the well distal from the first edge of the gate.

Abstract: A circuit device that includes a gate overlying an area of a semiconductor substrate, a well formed in the substrate proximate a first edge of the gate and doped with a first concentration of a first dopant, a channel region doped with a first concentration of a second dopant underlying a portion of the gate adjacent the well, a non-conducting region formed in the first portion of the well, and a contact to the second portion of the well distal from the first edge of the gate.