Patents by Inventor Adarsh RAJASHEKHAR

Adarsh RAJASHEKHAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139949
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR
  • Publication number: 20220139960
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of charge storage elements, a vertical semiconductor channel, a ferroelectric material layer located between the vertical stack of charge storage elements and the vertical semiconductor channel, and a blocking dielectric layer located between the ferroelectric material layer and the vertical semiconductor channel. A tunneling dielectric layer is located between at least one of the electrically conductive layers and the vertical stack of charge storage elements.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: Ramy Nashed Bassely SAID, Adarsh RAJASHEKHAR, Senaka KANAKAMEDALA, Raghuveer S. MAKALA
  • Publication number: 20220130853
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 28, 2022
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
  • Patent number: 11309332
    Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Rahul Sharangpani, Seung-Yeul Yang, Fei Zhou
  • Patent number: 11309301
    Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar
  • Patent number: 11302716
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 12, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Fei Zhou, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang
  • Patent number: 11282848
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 22, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Fei Zhou, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang
  • Publication number: 20220052073
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of in-process composite layers and sacrificial material layers including a lower insulating layer, a sacrificial spacer layer including silicon nitride or a semiconductor material, and an upper insulating layer, forming a memory opening vertically extending through the vertical stack, forming a memory opening fill structure in the memory opening, the memory opening fill structure including an in-process memory film and a vertical semiconductor channel, forming backside trenches through the alternating stack, replacing the sacrificial material layers with electrically conductive layers by removing the sacrificial material layers to form backside recesses and by depositing an electrically conductive material in the backside recesses, and converting the in-process composite layers into composite insulating layers by removing the sacrificial spacer layers to form lateral cavities and by optionally depositing replacement di
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Keigo KITAZAWA, Ippei YASUDA, Adarsh RAJASHEKHAR
  • Patent number: 11239254
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 1, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Seung-Yeul Yang
  • Patent number: 11239253
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 1, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou
  • Patent number: 11217532
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 4, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Tatsuya Hinoue, Tomoyuki Obu, Tomohiro Uno, Yusuke Mukae
  • Publication number: 20210408031
    Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR
  • Publication number: 20210407943
    Abstract: A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 30, 2021
    Inventors: Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Joyeeta NAG
  • Patent number: 11201139
    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 14, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Senaka Kanakamedala, Fei Zhou
  • Publication number: 20210375848
    Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: Fei ZHOU, Raghuveer S. MAKALA, Rahul SHARANGPANI, Adarsh RAJASHEKHAR
  • Publication number: 20210358942
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Adarsh RAJASHEKHAR, Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Yanli ZHANG
  • Publication number: 20210358952
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Raghuveer S. Makala, Yanli ZHANG, Fei ZHOU, Rahul SHARANGPANI, Adarsh RAJASHEKHAR, Seung-Yeul YANG
  • Publication number: 20210358931
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Raghuveer S. MAKALA, Yanli ZHANG, Fei ZHOU, Rahul SHARANGPANI, Adarsh RAJASHEKHAR, Seung-Yeul YANG
  • Patent number: 11177280
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Yanli Zhang
  • Patent number: 11145628
    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 12, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Senaka Kanakamedala, Fei Zhou