Abstract: Techniques for reducing the probability of spinlock and/or reducing the time that a virtual central processing unit (CPU) may hold a lock are provided. In one embodiment, a computer-implemented method includes determining that an executing virtual CPU is holding a lock for exclusive use of a resource, and scheduling the executing virtual CPU to run for up to a specified time period before de-scheduling the executing virtual CPU. In one embodiment, the executing virtual CPU holding the lock writes a value to a register to indicate that the executing virtual CPU is holding the lock.

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Abstract: In a computer comprising a plurality of integrated circuits (ICs), each IC may be connected to all other ICs via a respective point-to-point interconnect. A source IC divides the data to be transmitted to a destination IC for a transaction to generate multiple data cells so that each data cell includes a different portion of the data. The source IC transmits one of the data cells to the destination IC and remaining data cells to intermediate ICs, wherein an intermediate IC is an IC other than the source IC or the destination IC. The intermediate ICs forward the remaining data cells to the destination IC.

Abstract: Disclosed herein is an apparatus configured to log transactions of a translation lookaside buffer (TLB) into a software-accessible buffer. The apparatus includes a memory management unit (MMU) configured to translate a logical memory address to a physical memory address for accessing a physical memory. The apparatus also includes a TLB configured to store a plurality of entries, where each entry includes a logical memory page address and an associated physical memory page address. The apparatus further includes a software-accessible buffer and a TLB event logging circuit configured to detect an event associated with an entry of the TLB and store information regarding the detected event in the software-accessible buffer.

Abstract: Disclosed herein are techniques for balancing and reducing the number of write operations performed to each physical memory page of a storage-class memory. In one embodiment, a method includes tracking a count of write operations performed to each physical memory page or subpage of the storage-class memory using a memory management unit, a memory controller, a hypervisor, or an operating system, and selectively allocating physical memory pages of the storage-class memory with the least counts of write operations to a virtual machine or an operating system process using a ranking of the physical memory pages of the storage-class memory determined based at least partially on the count of write operations performed to each physical memory page or subpage of the storage-class memory.

Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. A hypervisor may clear the dirty pages and schedule the copy operations of the modified pages in a processing engine for copying to a target device. In one embodiment, before initiating the copy operation, the processing engine may check if the page has been modified again and omit the copy operation if the page has been modified again.

Abstract: In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

Abstract: Described herein is a hybrid approach to error reporting, using a combination of hardware and software, for peripheral component interconnect (PCI) express devices. The device hardware detects an error on a packet, where the packet is for a transaction and received from a host computer. Upon detecting the error, the device hardware generates an interrupt that is processed in software. In certain embodiments, the software based processing involves determining, based on the packet, that the transaction is directed to an address space of an emulated configuration register. The software based processing further involves identifying a function as being associated with the error, determining attributes associated with the error, and storing the attributes and an identifier associated with the function in a location available to the device hardware, thereby enabling the device hardware to report the attributes and identifier to the host computer.

Abstract: Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.

Abstract: In a memory controller, a prefetch indication can be sent to memory to prepare the memory for a potential future read or write. Statistics can be used to select when such a prefetch should occur. The prefetch can occur without any read or write command being commenced. As a result, the memory controller predicts when to perform the prefetch. Some examples of when a prefetch can be sent include when there are other requests for the same memory page, or how often the page is requested. The page can remain open to prevent it from closing until the relevant read or write arrives. In the case that a read or write does not occur after a predetermined period of time, then a precharge can be performed to release the memory page.

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decompression in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decompression engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decompression engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decompression engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. A hypervisor can queue the copy operations in a processing engine. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. In one embodiment, the processing engine may clear a dirty page just before performing the copy operation of the modified page to a target device, thus extending the window of time to capture any future writes to that page.

Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.

Abstract: Interfaces of a compute node on a printed circuit board can be secured by obfuscating the information communicated over the interfaces. Data to be communicated between the compute node and a device on the printed circuit board using an interface can be encrypted, and an address corresponding to the data to be communicated can be scrambled. In addition, the compute node can be the root of trust which can provide secure boot of different components using an on-chip mechanism, and without relying on external devices.

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

Abstract: Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.

Abstract: In various implementations, provided are systems and methods for an integrated circuit implementing a processor that can include a rate limiting circuit that attempts to fairly distribute processor memory bandwidth between transaction generators in the processor. The rate limiting circuit can maintain a count of tokens for each transaction generator, where a transaction generator can only transmit a transaction when the transaction generator has enough tokens to do so. Each transaction generator can send a request to the rate limiting circuit when the transaction generator wants to transmit a transaction. The rate limiting circuit can then check whether the transaction generator has sufficient tokens to transmit the transaction. When the transaction generator has enough tokens, the rate limiting circuit will allow the transaction to enter the interconnect. When the transaction generator does not have enough tokens, the rate limiting circuit will not allow the transaction to enter the interconnect.

Abstract: An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.

Abstract: A power analysis system for an integrated circuit device design can use machine learning to determine an estimated power consumption of the design. In various examples, the system can generate workloads for a power projection tool, which can include less than all the data of a full suite of power projection tests. The results from the power projection tool can be used to train a machine learning data model. From the results, the data model can learn the functions of the design by grouping together cells that are triggered together by the same signals. The data model can also learn estimated power consumption for each of the functions. The output of the data model can then be used to configure a design testing tool, which can run tests on the design. The output of the tests can then be used to compute an estimated overall power consumption for the design.