Abstract: A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.

Abstract: In some embodiments, a compensated power detector can include a power detector that includes a first detection cell having a bias input and an output, and a second detection cell having a signal input, a bias input and an output. The power detector can further include an error amplifier having a first input coupled to the output of the first detection cell, and a second input for receiving a reference voltage. The error amplifier can be configured to provide an output voltage to each of the bias inputs of the first and second detection cells, such that an output of the second detection cell is representative of power of a radio-frequency signal received at the signal input with an adjustment for one or more non-signal effects as measured by the first detection cell and the error amplifier.

Abstract: A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, and a power amplifier. The LDO voltage regulator, reference current generator, and power amplifier are integrated on a first semiconductor die.

Abstract: A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.

Abstract: In some embodiments, a compensated power detector can include a power detector that includes a first detection cell having a bias input and an output, and a second detection cell having a signal input, a bias input and an output. The power detector can further include an error amplifier having a first input coupled to the output of the first detection cell, and a second input for receiving a reference voltage. The error amplifier can be configured to provide an output voltage to each of the bias inputs of the first and second detection cells, such that an output of the second detection cell is representative of power of a radio-frequency signal received at the signal input with an adjustment for one or more non-signal effects as measured by the first detection cell and the error amplifier.

Abstract: A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, and a power amplifier. The LDO voltage regulator, reference current generator, and power amplifier are integrated on a first semiconductor die.

Abstract: A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, a power amplifier, and a voltage reference configured to provide a reference voltage to the LDO voltage regulator and the reference current generator. The LDO voltage regulator, reference current generator, power amplifier, and voltage reference are integrated on a first semiconductor die.

Abstract: A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.

Abstract: A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.

Abstract: Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.

Abstract: A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

Abstract: A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, a power amplifier, and a voltage reference configured to provide a reference voltage to the LDO voltage regulator and the reference current generator. The LDO voltage regulator, reference current generator, power amplifier, and voltage reference are integrated on a first semiconductor die.

Abstract: A broadband amplifier assembly is provided that includes a fixed gain amplifier coupled to an adjustable attenuator which is further coupled to a power amplifier. The adjustable attenuator includes a plurality of attenuation cells directly coupled in series between the input and the output of the adjustable attenuator.

Abstract: An attenuation cell is provided for use in a switched attenuator. The attenuation cell includes an attenuation path that has an input, a first switch, a resistive network, a second switch, and an output. The resistive network provides a desired attenuation from the input to the output. The attenuation cell also includes a bypass path in parallel with the attenuation path with a bypass switch between the input and the output. The attenuation cell also has a shunt switch coupled between the resistive network and a reference node to selectively connect the resistive network to the reference node.

Abstract: Systems and methods are provided for reducing the effects of an impedance mismatch between a communications system and a shared communications medium. A communication system, such as a transceiver within a cable modem, switches between various operating modes including a transmit mode, a receive mode, and a standby mode. The standby mode may be used while the transceiver is in an idle state between modes, such as while changing an amplifier gain states in between transmissions. While transitioning between modes, the impedance presented by the communications system can temporarily fluctuate causing unwanted signal reflections to propagate out of the communications system and on to the shared medium. Circuitry within the communications system, such as transmission circuitry including an adjustable attenuator, may be placed into a hybrid attenuation-isolation mode during the transition causing the magnitude of any unwanted signal reflections to be attenuated and reducing the impact on the shared medium.

Abstract: Systems and methods for suppressing transient outputs from an amplifier system are provided. An amplifier having a plurality of bias levels may be controlled to initiate a change in the level of a bias signal provided to the amplifier. The level of the bias signal is ramped from an initial bias level to a final bias level over numerous steps. The steps include at least one step in which the level of the bias signal is between the initial bias level and the final bias level. An amplifier system having multiple stages may be controlled to enable each stage and selectively couple each stage in a sequence that couples an output stage to an output terminal at the completion of the sequence.

Abstract: Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

Abstract: In some embodiments, a compensated power detector can include a power detector that includes a first detection cell having a bias input and an output, and a second detection cell having a signal input, a bias input and an output. The power detector can further include an error amplifier having a first input coupled to the output of the first detection cell, and a second input for receiving a reference voltage. The error amplifier can be configured to provide an output voltage to each of the bias inputs of the first and second detection cells, such that an output of the second detection cell is representative of power of a radio-frequency signal received at the signal input with an adjustment for one or more non-signal effects as measured by the first detection cell and the error amplifier.