Patents by Inventor Ahmed A. Emira

Ahmed A. Emira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7728550
    Abstract: An electrical circuit and method of power management of a cellular telephone includes a battery adapted to produce a battery voltage; a LDO regulator operatively connected to the battery and adapted to provide a constant supply voltage from the battery voltage; and a DC-DC converter operatively connected to the LDO regulator, wherein the DC-DC converter is adapted to step down the constant supply voltage to a lower voltage level, wherein the LDO regulator and the DC-DC converter are embedded on a single integrated circuit chip. The constant supply voltage equals 3.6V at an output of the LDO, and the constant supply voltage is applied to an input of the DC-DC converter. Moreover, the battery voltage equals at most 5.5V.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 1, 2010
    Assignee: Newport Media, Inc.
    Inventors: Frank Carr, Ahmed A. Emira, Hassan Elwan
  • Patent number: 7697901
    Abstract: A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: April 13, 2010
    Assignee: ST-Ericsson SA
    Inventors: Srinath Sridharan, Ahmed Emira, Aria Eshraghi, David Welland
  • Patent number: 7592791
    Abstract: A DC-DC converter and method of improving the efficiency of a DC-DC converter at low load current levels using pulse skipping modulation (PSM) with controllable burst duration NTclk, where Tclk is the clock cycle interval. As the average load current increases, the time between bursts decreases so that average inductor current matches the load current. The burst duration is kept around NTclk by controlling the duty cycle of the output switches. The higher the load current, the higher is the duty cycle of the output switches. No current sensing is needed. The optimum burst duration for best efficiency curve is a function of the load capacitor.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: September 22, 2009
    Assignee: Newport Media, Inc.
    Inventor: Ahmed A. Emira
  • Patent number: 7592863
    Abstract: A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: September 22, 2009
    Assignee: Newport Media, Inc.
    Inventors: Hassan Elwan, Amr Fahim, Edward Youssounan, Ahmed A. Emira, Dejun Wang
  • Publication number: 20090115458
    Abstract: A complementary metal oxide semiconductor (CMOS) comparator circuit includes a plurality of p-type metal-oxide-semiconductor (PMOS) transistors receiving an input voltage signal, a plurality of n-type metal-oxide-semiconductor (NMOS) transistors operatively connected to the PMOS transistors and adapted to receive the input voltage signal, and an inverter adapted to invert the input voltage signal into an output voltage signal. An effective aspect ratio of the PMOS and NMOS transistors may be dependent on the level of the output voltage signal from the inverter. When a digital output of the inverter is “1”, the effective aspect ratio of the NMOS transistor is increased by turning on a second NMOS transistor, and a threshold voltage of the inverter is decreased.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventors: Frank Carr, Ahmed A. Emira
  • Publication number: 20090046487
    Abstract: A DC-DC converter and method of improving the efficiency of a DC-DC converter at low load current levels using pulse skipping modulation (PSM) with controllable burst duration NTclk, where Tclk is the clock cycle interval. As the average load current increases, the time between bursts decreases so that average inductor current matches the load current. The burst duration is kept around NTclk by controlling the duty cycle of the output switches. The higher the load current, the higher is the duty cycle of the output switches. No current sensing is needed. The optimum burst duration for best efficiency curve is a function of the load capacitor.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 19, 2009
    Inventor: Ahmed A. Emira
  • Publication number: 20090021228
    Abstract: An electrical circuit and method of power management of a cellular telephone includes a battery adapted to produce a battery voltage; a LDO regulator operatively connected to the battery and adapted to provide a constant supply voltage from the battery voltage; and a DC-DC converter operatively connected to the LDO regulator, wherein the DC-DC converter is adapted to step down the constant supply voltage to a lower voltage level, wherein the LDO regulator and the DC-DC converter are embedded on a single integrated circuit chip. The constant supply voltage equals 3.6V at an output of the LDO, and the constant supply voltage is applied to an input of the DC-DC converter. Moreover, the battery voltage equals at most 5.5V.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 22, 2009
    Inventors: Frank Carr, Ahmed A. Emira, Hassan Elwan
  • Publication number: 20080297239
    Abstract: A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Inventors: Hassan Elwan, Amr Fahim, Edward Youssounan, Ahmed A. Emira, Dejun Wang
  • Publication number: 20070072558
    Abstract: A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.
    Type: Application
    Filed: March 30, 2006
    Publication date: March 29, 2007
    Inventors: Srinath Sridharan, Ahmed Emira, Aria Eshraghi, David Welland