Patents by Inventor Ahmed Safwat Mohamed Aboelenein Elmallah

Ahmed Safwat Mohamed Aboelenein Elmallah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171167
    Abstract: A digitally controlled delay device includes a plurality of first delay stages connected in series between a first input port and a first output port, and a plurality of second delay stages connected in series between a second input port and a second output port. Each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements. A controller performs complementary control based on a digital control signal by controlling one or more of the plurality of first delay elements to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 23, 2024
    Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Amr Tarek Ahmed Abdelrazik Khashaba, Mohammed Mohsen Abdulsalam Abdullatif, Tamer Mohammed Ali
  • Publication number: 20240171166
    Abstract: A system to operate as a phase locked loop (PLL) includes a frequency synthesizer in a feedback path of the PLL and a delay line arranged to receive an output of the frequency synthesizer. A retimer subsystem is arranged to receive the output of the frequency synthesizer. A digitally controlled delay line (DCDL) is arranged to receive an output of the retimer. A phase detector is arranged to receive an output of the delay line and an output of the DCDL and to provide an error signal indicating a difference in phase of the output of the delay line relative to the output of the DCDL. A controller causes closed loop operation of the PLL during a normal operational mode and open loop operation during a calibration mode during which gain of the DCDL, defining a relationship between a control code and a resulting delay, is calibrated.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 23, 2024
    Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Amr Tarek Ahmed Abdelrazik Khashaba, Mohammed Mohsen Abdulsalam Abdullatif, Tamer Mohammed Ali
  • Publication number: 20240171181
    Abstract: The techniques described herein relate to duty cycle error calibration. An example apparatus includes a multi-modulus divider (MMD) circuit configured to receive a first digital code corresponding to a first time delay and included in a first plurality of digital codes associated with a first range of time delays, divide a clock signal by a divisor to generate a divided clock signal, and delay the divided clock signal by the first time delay to generate a delayed clock signal. The apparatus may further include a digitally controlled delay line (DCDL) circuit configured to receive a second digital code corresponding to a second time delay and included in a second plurality of digital codes associated with a second range of time delays, and delay the delayed clock signal by the second time delay to generate a feedback clock signal to reduce a difference between the feedback and a reference clock signal.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 23, 2024
    Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Mohammed Mohsen Abdulsalam Abdullatif, Tamer Mohammed Ali
  • Publication number: 20240171165
    Abstract: A circuit or reducing fractional spurs comprises a digital to time converter (DTC) comprising multiple delay stages electrically coupled to one another in series, configured such that each delay stage is binary switched till the code exceeds cell range and then it is fully turned ON, and thereafter it is moved to the next stage, each delay stage comprising a digitally controlled delay line (DCDL) having code-dependent integrated nonlinearity (INL), with the maximal value of the INL occuring at a mid-code position; and an offset stage comprising the DCDL electrically coupled to the DTC in series, configured to generate random codes for each required time delay of the DTC to ensure the probability of landing at the mid-code position is reduced and landing point is kept as far away as possible from the mid-code position for every required time delay, thereby improving the INL and the fractional spurs.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 23, 2024
    Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Mohammed Mohsen Abdulsalam Abdullatif, Tamer Mohammed Ali
  • Publication number: 20240162906
    Abstract: The techniques described herein relate to systems, apparatus, articles of manufacture, and methods for optimum loop gain calibration for clock data recovery and phase locked loop. An example apparatus includes a phase detector with a phase detector output and configured to generate an error signal representative of a difference between an input signal and a feedback signal. The apparatus further includes a calibrator circuit with a calibrator input coupled to the phase detector output and configured to determine correlation value associated with the error signal, and determine a gain value based on an adjustment of an absolute value of the correlation value by a pseudorandom binary sequence signal.
    Type: Application
    Filed: October 17, 2023
    Publication date: May 16, 2024
    Applicant: MediaTek Inc.
    Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Mohammed Mohsen Abdulsalam Abdullatif, Tamer Mohammed Ali
  • Publication number: 20240162907
    Abstract: The techniques described herein relate to digitally controlled delay line gain calibration using error injection. An example apparatus includes a digitally controlled delay line (DCDL) with a DCDL output and configured to: receive a clock signal to be output from a voltage-controlled oscillator, and delay the clock signal to generate a first delayed clock signal. The apparatus further includes an error injection circuit with a first error injection input and a second error injection input, the first error injection input coupled to the DCDL output. The apparatus additionally includes a phase controller with a phase controller output coupled to the second error injection input, the phase controller configured to, in response to a pseudorandom binary sequence signal, instruct the error injection circuit to generate a second delayed clock signal based on a delay of the first delayed clock signal.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 16, 2024
    Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Amr Tarek Ahmed Abdelrazik Khashaba, Mohammed Mohsen Abdulsalam Abdullatif, Tamer Mohammed Ali
  • Publication number: 20240146326
    Abstract: The techniques described herein relate to analog-assisted feed-forward equalizers. An example apparatus includes a first charge element digital-to-analog converter (DAC) including a first plurality of charge storage elements configured to store first samples of charge based on respective first portions of a digital input signal, and generate, based on the first samples, a first analog output signal proportional to the first portions. The apparatus further includes a second charge element DAC coupled to the first charge element DAC and including a second plurality of charge storage elements configured to store second samples of charge based on respective second portions of the digital input signal, and generate, based on the second samples, a second analog output signal proportional to the second portions, and wherein the coupling of the first and second outputs generates a third analog output signal based on a combination of the first and second analog output signals.
    Type: Application
    Filed: September 28, 2023
    Publication date: May 2, 2024
    Applicant: Media Tek Inc.
    Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah, Amed Othman Mohamed Mohamed ElShater, Tamer Mohammed Ali
  • Publication number: 20230403015
    Abstract: A multi-path voltage-controlled oscillator (VCO) includes a VCO core circuit and a control voltage generator circuit. The VCO core circuit includes a varactor that has a control node for receiving a control voltage. The control voltage generator circuit receives at least one proportional path (P-path) control input and an integral path (I-path) control input, and generates and outputs the control voltage to the control node of the varactor according to the at least one P-path control input and the I-path control input.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 14, 2023
    Applicant: MEDIATEK INC.
    Inventors: Tsz-Bin Liu, Mohammed Mohsen Abdulsalam Abdullatif, Ahmed Safwat Mohamed Aboelenein Elmallah, Mohammed Tamer Ali