Patents by Inventor AJ Kleinosowski
AJ Kleinosowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8354858Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: GrantFiled: January 8, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 8271912Abstract: A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.Type: GrantFiled: March 19, 2008Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Matthew R. Ellavsky, AJ KleinOsowski, Scott M. Willenborg
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Patent number: 8211741Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: GrantFiled: June 28, 2011Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20110263101Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: ApplicationFiled: June 28, 2011Publication date: October 27, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Patent number: 8017934Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: GrantFiled: August 4, 2010Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20110102042Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: ApplicationFiled: January 8, 2011Publication date: May 5, 2011Applicant: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 7888959Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: GrantFiled: September 19, 2007Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 7881135Abstract: A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.Type: GrantFiled: February 27, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, Alan J. Drake, Fadi H. Gebara, John P. Keane, AJ Kleinosowski
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Publication number: 20100295025Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: ApplicationFiled: August 4, 2010Publication date: November 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20100271057Abstract: A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.Type: ApplicationFiled: February 27, 2007Publication date: October 28, 2010Inventors: Ethan H. Cannon, Alan J. Drake, Fadi H. Gebara, John P. Keane, AJ KleinOsowski
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Patent number: 7786466Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: GrantFiled: January 11, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Patent number: 7774732Abstract: A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on particle migration within the silicon substrate. The method starts with an initial placement, identifies the objects for which radiation tolerance is desired, determines whether any of those objects and, if so, moves the relevant objects to increase the spacing. An exemplary threshold for contemporary CMOS device technologies is 5 ?m. The objects can be moved by vertically and/or horizontally shifting away from a reference point of the integrated circuit. The critical objects may include triplicated (redundant) structures, clock control latches, or a reset bit. The method can be used in conjunction with other placement optimizations such as area, power and timing.Type: GrantFiled: August 14, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: AJ KleinOsowski, Scott M. Willenborg, Bruce B. Winter
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Patent number: 7734970Abstract: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).Type: GrantFiled: July 6, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Alan J. Drake, AJ KleinOsowski, Andrew K. Martin
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Patent number: 7725870Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.Type: GrantFiled: August 14, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Mark R. Beckenbaugh, AJ KleinOsowski, Eric J. Lukes
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Patent number: 7698681Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.Type: GrantFiled: August 14, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Mark R. Beckenbaugh, AJ KleinOsowski, Eric J. Lukes, Byron D. Scott
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Publication number: 20090241073Abstract: A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Inventors: Matthew R. Ellavsky, Aj KleinOsowski, Scott M. Willenborg
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Patent number: 7590907Abstract: A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.Type: GrantFiled: July 6, 2008Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: Alan J. Drake, AJ KleinOsowski, Andrew K. Martin
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Publication number: 20090179193Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: ApplicationFiled: January 11, 2008Publication date: July 16, 2009Inventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20090134925Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: ApplicationFiled: September 19, 2007Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Publication number: 20090049418Abstract: A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on particle migration within the silicon substrate. The method starts with an initial placement, identifies the objects for which radiation tolerance is desired, determines whether any of those objects and, if so, moves the relevant objects to increase the spacing. An exemplary threshold for contemporary CMOS device technologies is 5 ?m. The objects can be moved by vertically and/or horizontally shifting away from a reference point of the integrated circuit. The critical objects may include triplicated (redundant) structures, clock control latches, or a reset bit. The method can be used in conjunction with other placement optimizations such as area, power and timing.Type: ApplicationFiled: August 14, 2007Publication date: February 19, 2009Inventors: AJ KleinOsowski, Scott M. Willenborg, Bruce B. Winter