Abstract: Methods and systems for controlling access to a host processor is disclosed. One exemplary method comprises the steps of receiving a plurality of signaling packets and controlling access to a host processor, via a first and a second path, for at least a portion of the packets in accordance with a bandwidth limit for the respective path. An exemplary system comprises: a host processor; and a traffic manager coupled to the host processor via a first path and a second path. The traffic manager is configured to communicate at least a portion of the packets to the host processor via a selected one of the paths. The traffic manager is further configured to regulate traffic along the first path such that the bandwidth limit of the first path is respected, and to regulate traffic along the second path such that the bandwidth limit of the second path is respected.

Abstract: A system and method for determining a destination for an Internet protocol packet. Generally, with reference to the structure of the system, the system utilizes a memory and a processor.

Abstract: Methods and systems for controlling access to a host processor is disclosed. One exemplary method comprises the steps of receiving a plurality of signaling packets and controlling access to a host processor, via a first and a second path, for at least a portion of the packets in accordance with a bandwidth limit for the respective path. An exemplary system comprises: a host processor; and a traffic manager coupled to the host processor via a first path and a second path. The traffic manager is configured to communicate at least a portion of the packets to the host processor via a selected one of the paths. The traffic manager is further configured to regulate traffic along the first path such that the bandwidth limit of the first path is respected, and to regulate traffic along the second path such that the bandwidth limit of the second path is respected.

Abstract: A system and method for determining a destination for an Internet protocol packet. Generally, with reference to the structure of the system, the system utilizes a memory and a processor. The processor is instructed by the memory to perform the steps of: searching the memory for a destination Internet protocol address associated with the Internet protocol packet; reading a destination media access control address identified by the destination Internet protocol address; dropping the Internet protocol packet if a value of the destination media access control address is zero; and adding the media access control address to the Internet protocol packet as the destination of the packet, if the destination media access control address is not equal to zero. In addition, the memory is preferably a content addressable memory.

Abstract: A system and method for determining a source of an Internet protocol packet (IP). Generally, the system comprises a memory and a processor. The processor compares a destination address of the IP packet to a first destination address stored within a first destination address cell of the memory, and compares a destination port of the IP packet to a first destination port stored within a first destination port cell of the memory. The network processor also compares a source address of the IP packet to a first source address stored within a first source address cell of the memory, and compares a source port of the IP packet to a first source port stored within a first source port cell of the memory, wherein the stored first source address and the stored first source port are associated with the stored first destination address and the stored first destination port.