Patents by Inventor Ajaya V. Durg
Ajaya V. Durg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118892Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Swagath VENKATARAMANI, Dipankar DAS, Ashish RANJAN, Subarno BANERJEE, Sasikanth AVANCHA, Ashok JAGANNATHAN, Ajaya V. DURG, Dheemanth NAGARAJ, Bharat KAUL, Anand RAGHUNATHAN
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Publication number: 20220050683Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.Type: ApplicationFiled: October 26, 2021Publication date: February 17, 2022Inventors: Swagath VENKATARAMANI, Dipankar DAS, Ashish RANJAN, Subarno BANERJEE, Sasikanth AVANCHA, Ashok JAGANNATHAN, Ajaya V. DURG, Dheemanth NAGARAJ, Bharat KAUL, Anand RAGHUNATHAN
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Patent number: 10963038Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.Type: GrantFiled: January 21, 2019Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
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Patent number: 10474219Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.Type: GrantFiled: November 30, 2015Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Arojit Roychowdhury, Ramanathan Sethuraman, Ajaya V. Durg, Rakesh A. Ughreja
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Publication number: 20190303743Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.Type: ApplicationFiled: September 27, 2016Publication date: October 3, 2019Inventors: Swagath VENKATARAMANI, Dipankar DAS, Ashish RANJAN, Subarno BANERJEE, Sasikanth AVANCHA, Ashok JAGANNATHAN, Ajaya V. DURG, Dheemanth NAGARAJ, Bharat KAUL, Anand RAGHUNATHAN
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Publication number: 20190155370Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.Type: ApplicationFiled: January 21, 2019Publication date: May 23, 2019Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
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Patent number: 10282344Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.Type: GrantFiled: June 4, 2015Date of Patent: May 7, 2019Assignee: INTEL CORPORATIONInventors: Sundar Iyer, Rajasekaran Andiappan, Ajaya V. Durg, Kenneth P. Foust, Bruce L. Fleming
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Patent number: 10275853Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.Type: GrantFiled: April 15, 2015Date of Patent: April 30, 2019Assignee: Intel CorporationInventors: Ramanathan Sethuraman, Arojit Roychowdhury, Ajaya V. Durg, Rajeev D. Muralidhar
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Patent number: 10198065Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.Type: GrantFiled: April 24, 2017Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
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Publication number: 20170336854Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 30, 2015Publication date: November 23, 2017Applicant: Intel CorporationInventors: Arojit Roychowdhury, Ramanathan Sethuraman, Ajaya V. Durg, Rakesh A. Ughreja
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Publication number: 20170228014Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
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Patent number: 9665153Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.Type: GrantFiled: March 21, 2014Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
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Publication number: 20170103036Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.Type: ApplicationFiled: June 4, 2015Publication date: April 13, 2017Applicant: Intel CorporationInventors: Sundar Iyer, Rajasekaran Andiappan, Ajaya V. Durg, Kenneth P. Foust, Bruce L. Fleming
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Patent number: 9620088Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.Type: GrantFiled: March 11, 2015Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Vasudev Bibikar, Rajesh Poornachandran, Ajaya V. Durg, Arpit Shah, Anil K. Sabbavarapu, Nabil F. Kerkiz, Quang T. Le, Ryan R. Pinto, Moorthy Rajesh, James A. Bish, Ranjani Sridharan
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Publication number: 20160307291Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.Type: ApplicationFiled: April 15, 2015Publication date: October 20, 2016Applicant: INTEL CORPORATIONInventors: Ramanathan Sethuraman, Arojit Roychowdhury, Ajaya V. Durg, Rajeev D. Muralidhar
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Publication number: 20160267883Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.Type: ApplicationFiled: March 11, 2015Publication date: September 15, 2016Inventors: Vasudev Bibikar, Rajesh Poornachandran, Ajaya V. Durg, Arpit Shah, Anil K. Sabbavarapu, Nabil F. Kerkiz, Quang T. Le, Ryan R. Pinto, Moorthy Rajesh, James A. Bish, Ranjani Sridharan
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Publication number: 20150268711Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Inventors: Sundar Ramani, Arvind Raman, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg, Samudyatha Chakki
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Patent number: 6563536Abstract: A method includes generating a noise frame of data that is representative of a dark current image. Video frames of data are generated that represent video images. The video frames include noise. Information from the noise frame is used to compensate for the noise.Type: GrantFiled: May 20, 1998Date of Patent: May 13, 2003Assignee: Intel CorporationInventors: Oleg B. Rashkovskiy, William W. Macy, Ajaya V. Durg
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Patent number: 6212304Abstract: A method and apparatus for processing an image is described. A first area having a first value is selected. A second value for a second area surrounding the first area is determined. The first and second values are compared with a predetermined threshold. The first value is transformed according to the comparison.Type: GrantFiled: July 6, 1998Date of Patent: April 3, 2001Assignee: Intel Corp.Inventors: Ajaya V. Durg, Oleg Rashkovskiy
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Patent number: 6122744Abstract: A method includes determining an operating frequency of a processor. Based on the operating frequency, a routine is selected from a group of at least two routines, and the selected routine is executed. The routine may also be selected based on an unused processing bandwidth that is available to the processor.Type: GrantFiled: May 20, 1998Date of Patent: September 19, 2000Assignee: Intel CorporationInventors: Oleg B. Rashkovskiy, Ajaya V. Durg