Patents by Inventor Ajey Poovannummoottil Jacob

Ajey Poovannummoottil Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468456
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Patent number: 10468084
    Abstract: The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob
  • Patent number: 10468083
    Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
  • Patent number: 10461173
    Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Xuan Anh Tran, Hui Zang, Bala Haran, Suryanarayana Kalaga
  • Patent number: 10444433
    Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A tapered feature composed of a dielectric material is arranged over the waveguide. The tapered feature includes a sidewall that is angled relative to a longitudinal axis of the waveguide.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Abu Thomas, Ajey Poovannummoottil Jacob, Kenneth J. Giewont, Karen Nummy, Andreas Stricker, Bo Peng
  • Publication number: 20190310399
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with structured cladding and methods of manufacture. A structure includes: a grating coupler in a dielectric material; a back end of line (BEOL) multilayer stack over the dielectric material; and a multi-layered cladding structure of alternating materials directly on the BEOL multilayer stack.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Ajey Poovannummoottil JACOB, Yusheng BIAN
  • Patent number: 10436982
    Abstract: Structures including waveguide bends, methods of fabricating a structure that includes waveguide bends, and systems that integrate optical components containing different materials. A first waveguide bend is contiguous with a waveguide, and a second waveguide bend is spaced in a vertical direction from the first waveguide bend. The second waveguide bend has an overlapping arrangement with the first waveguide bend in a lateral direction.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Publication number: 20190304528
    Abstract: The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Inventors: Akhilesh R. JAISWAL, Ajey Poovannummoottil JACOB
  • Patent number: 10429582
    Abstract: Waveguide-to-waveguide couplers, systems that include waveguide-to-waveguide couplers, and methods of fabricating waveguide-to-waveguide couplers. A first waveguide is coupled to a first waveguide taper, and a second waveguide is coupled to a second waveguide taper. The first waveguide and the first waveguide taper are comprised of silicon, and the second waveguide and the second waveguide taper are comprised of silicon nitride. The second waveguide and the second waveguide taper are arranged in a vertical direction over the first waveguide and the first waveguide taper.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Steven M. Shank
  • Patent number: 10429581
    Abstract: Structures for a polarization splitter and methods of forming a polarization splitter. A multi-mode interference region includes a first waveguide and a second waveguide arranged in a stack over the first waveguide. First and second input ports are connected with the multi-mode interference region. First and second output ports are connected with the multi-mode interference region.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abu Thomas, Yusheng Bian, Ajey Poovannummoottil Jacob
  • Patent number: 10411069
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: September 10, 2019
    Assignee: Globalfoundries, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Publication number: 20190259808
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 22, 2019
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Publication number: 20190259809
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 22, 2019
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Publication number: 20190259810
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 22, 2019
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Patent number: 10381406
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: August 13, 2019
    Assignee: Globalfoundries, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Patent number: 10325812
    Abstract: A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 10241269
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with multiple configurations and methods of manufacture. A structure includes: a grating coupler having a sawtooth configuration provided over a semiconductor slab; and a back end of line (BEOL) stack over the sawtooth configuration of the grating coupler.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Yusheng Bian
  • Patent number: 10186577
    Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 10185092
    Abstract: Structures for grating couplers and methods of fabricating a structure including grating couplers. A first grating coupler includes a first plurality of grating structures. An interconnect structure includes a first metallization level that is positioned over the first grating coupler. A second grating coupler includes a second plurality of grating structures that are arranged in the first metallization level to overlap with the first grating coupler. The second plurality of grating structures are composed of a metal.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Publication number: 20180286951
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a first semiconductor material and forming a plurality of vertically-oriented channel semiconductor (VOCS) structures on at least opposing lateral sidewall surfaces of the sacrificial mandrel structure, the VOCS structures comprising a second semiconductor material that is different than the first semiconductor material. In this example, the method also includes selectively removing the sacrificial mandrel structure relative to the VOCS structures and forming upper and lower source/drain regions in each of the VOCS structures and a gate structure around each of the VOCS structures.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventor: Ajey Poovannummoottil Jacob