Patents by Inventor Ajey Poovannummoottil Jacob

Ajey Poovannummoottil Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180286951
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a first semiconductor material and forming a plurality of vertically-oriented channel semiconductor (VOCS) structures on at least opposing lateral sidewall surfaces of the sacrificial mandrel structure, the VOCS structures comprising a second semiconductor material that is different than the first semiconductor material. In this example, the method also includes selectively removing the sacrificial mandrel structure relative to the VOCS structures and forming upper and lower source/drain regions in each of the VOCS structures and a gate structure around each of the VOCS structures.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 10090385
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a first semiconductor material and forming a plurality of vertically-oriented channel semiconductor (VOCS) structures on at least opposing lateral sidewall surfaces of the sacrificial mandrel structure, the VOCS structures comprising a second semiconductor material that is different than the first semiconductor material. In this example, the method also includes selectively removing the sacrificial mandrel structure relative to the VOCS structures and forming upper and lower source/drain regions in each of the VOCS structures and a gate structure around each of the VOCS structures.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 10056453
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Srinivasa R. Banna, Deepak K. Nayak, Bartlomiej J. Pawlak
  • Patent number: 10056300
    Abstract: A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A PMOS FinFET device includes a second fin. The second fin includes a second strain relaxed buffer layer and a second channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A first gate structure is positioned around a portion of the NMOS fin. A second gate structure is positioned around a portion of the PMOS fin.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20180233413
    Abstract: A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 10026659
    Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Jody A. Fronheiser
  • Patent number: 9972537
    Abstract: One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9960257
    Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
  • Patent number: 9954104
    Abstract: An improved structure and methods of fabrication for finFET devices utilizing a cladding channel are disclosed. A staircase fin is formed where the fin comprises an upper portion of a first width and a lower portion of a second width, wherein the lower portion is wider than the upper portion. The narrower upper portion allows the cladding channel to be deposited and still have sufficient space for proper gate deposition, while the lower portion is wide to provide improved mechanical stability, which protects the fins during the subsequent processing steps.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 24, 2018
    Inventors: Ruilong Xie, Ajey Poovannummoottil Jacob
  • Publication number: 20180033700
    Abstract: A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A PMOS FinFET device includes a second fin. The second fin includes a second strain relaxed buffer layer and a second channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A first gate structure is positioned around a portion of the NMOS fin. A second gate structure is positioned around a portion of the PMOS fin.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 1, 2018
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20180026096
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 25, 2018
    Inventors: Ajey Poovannummoottil Jacob, Srinivasa R. Banna, Deepak K. Nayak, Bartlomiej J. Pawlak
  • Patent number: 9865682
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9864132
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon waveguide devices in integrated photonics and methods of manufacture. The integrated photonics structure includes: a localized region of negative thermal expansion (NTE) coefficient material formed within a trench; at least one photonics or CMOS component contacting with the negative thermal expansion (NTE) coefficient material; and cladding material formed above the at least one photonics or CMOS component.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Roderick A. Augur, Ajey Poovannummoottil Jacob, Steven M. Shank
  • Patent number: 9824935
    Abstract: A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9799767
    Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20170301589
    Abstract: A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 19, 2017
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20170263465
    Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.
    Type: Application
    Filed: May 18, 2017
    Publication date: September 14, 2017
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9754903
    Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj K. Patil, Min-hwa Chi, Ajey Poovannummoottil Jacob
  • Patent number: 9748387
    Abstract: One method disclosed includes forming first, second and third fins for a first NMOS device, a PMOS device and a second NMOS device, respectively. According to this method, the first fin consists entirely of the substrate material, the second and third fins comprise a lower substrate fin portion made of the substrate material and an upper fin portion made of a second semiconductor material and a third semiconductor material, respectively, wherein the second semiconductor material and the third semiconductor material are each different from the substrate material. The method also includes forming a semiconductor material cladding on the exposed upper portion of the third fin for the second NMOS FinFET device.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20170243791
    Abstract: One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.
    Type: Application
    Filed: February 24, 2016
    Publication date: August 24, 2017
    Inventor: Ajey Poovannummoottil Jacob