Patents by Inventor Ajey Poovannummoottil Jacob

Ajey Poovannummoottil Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9478663
    Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Yi Qi, Sylvie Mignot
  • Patent number: 9466664
    Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 11, 2016
    Assignees: STMICROELECTRONICS, INC., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, GLOBALFOUNDRIES INC.
    Inventors: Pierre Morin, Maud Vinet, Laurent Grenouillet, Ajey Poovannummoottil Jacob
  • Patent number: 9455140
    Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Murat Kerem Akarvardar
  • Patent number: 9455199
    Abstract: One illustrative method disclosed herein includes, among other things, forming a first fin for the PMOS device and a second fin for the NMOS device, wherein each of the first and second fins comprises a lower substrate fin portion and an upper fin portion that is made of semiconductor material that is different from that of the substrate, performing at least one process operation to form a first channel semiconductor material for the PMOS FinFET device that comprises a fully-strained, substantially defect-free substantially pure germanium material on a recessed upper surface of the upper fin portion of the first fin and form a second channel semiconductor material for the NMOS FinFET device that comprises a fully-relaxed substantially pure germanium material that is substantially defect free positioned above an upper surface of the lower substrate fin portion of the second fin.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20160268400
    Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 15, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem AKARVARDAR, Jody A. FRONHEISER, Ajey Poovannummoottil JACOB
  • Publication number: 20160260742
    Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Applicants: GLOBALFOUNDRIES Inc., STMICROELECTRONICS, INC.
    Inventors: Ajey Poovannummoottil JACOB, Kangguo CHENG, Bruce DORIS, Nicolas LOUBET, Prasanna KHARE, Rama DIVAKARUNI
  • Publication number: 20160254361
    Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 1, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven J. Bentley, Ajey Poovannummoottil Jacob, Chia-Yu Chen, Tenko Yamashita
  • Publication number: 20160254195
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Bruce Doris, Ali Khakifirooz
  • Patent number: 9431306
    Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 30, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Ali Khakifirooz, Kern Rim
  • Patent number: 9425315
    Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar
  • Patent number: 9425289
    Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar
  • Publication number: 20160225677
    Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches.
    Type: Application
    Filed: March 21, 2016
    Publication date: August 4, 2016
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Ali Khakifirooz, Kern Rim
  • Publication number: 20160225719
    Abstract: A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20160225676
    Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Jody A. Fronheiser
  • Publication number: 20160225870
    Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20160225659
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Ali Khakifirooz, Kern Rim
  • Publication number: 20160225542
    Abstract: Embodiments of the present disclosure relate to a solid-state supercapacitor. The solid-state supercapacitor includes a first electrode, a second electrode, and a solid-state ionogel structure between the first electrode and the second electrode. The solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode. Further, the solid-state ionogel structure substantially fills voids inside the first electrode and the second electrode.
    Type: Application
    Filed: November 13, 2014
    Publication date: August 4, 2016
    Applicant: INTEL CORPORATION
    Inventors: Bruce S. Dunn, Chi On Chui, Ajey Poovannummoottil Jacob, Daniel Membreno, Leland Smith
  • Publication number: 20160225674
    Abstract: One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of insulating material, forming an initial strain relaxed buffer layer such that it only partially fills the replacement fin cavities, implanting carbon into the initial strain relaxed buffer layer in the NMOS region, forming a channel semiconductor material on the initial strain relaxed buffer layer within the replacement fin cavities in both the NMOS region and the PMOS region to thereby define an NMOS fin comprised of the channel semiconductor material and a carbon-doped strain relaxed buffer layer and a PMOS fin comprised of the channel semiconductor material and the initial strain relaxed buffer layer and forming gate structures for the NMOS and PMOS devices.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9406803
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Murat Kerem Akarvardar, Steven Bentley
  • Publication number: 20160204261
    Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.
    Type: Application
    Filed: March 18, 2016
    Publication date: July 14, 2016
    Inventors: Ajey Poovannummoottil Jacob, Witold P. Maszara, Jody A. Fronheiser