Patents by Inventor Akihiko Chiba

Akihiko Chiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240074214
    Abstract: A semiconductor memory device includes a plurality of transistors arranged in a first direction, and arranged in a second direction and a first wiring layer disposed between a semiconductor substrate and a plurality of voltage supply wirings. Each of the plurality of transistors includes a source region and a drain region. The first wiring layer includes a plurality of first connecting portions disposed at positions overlapping with the plurality of source regions when viewed in a third direction and electrically connected to the plurality of source regions and the plurality of voltage supply wirings, a plurality of second connecting portions disposed at positions overlapping with the plurality of source regions when viewed in the third direction and electrically connected to a plurality of the drain regions and a plurality of conductive layers, and a passing wiring region disposed between a pair of the second connecting portions.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 29, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Nobuaki OKADA, Akihiko CHIBA, Kenichi MATOBA, Haruna SUGIURA
  • Publication number: 20240029797
    Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Inventors: Hiroyuki TAKENAKA, Akihiko CHIBA, Teppei HIGASHITSUJI, Kiyofumi SAKURAI, Hiroaki NAKASA, Youichi MAGOME
  • Patent number: 11872647
    Abstract: A production method of an additive manufactured object is provided. The method is an EB-based additive manufacturing method of spreading a pure copper powder, preheating the pure copper powder and thereafter partially melting the pure copper powder by scanning the pure copper powder with an electron beam, solidifying the pure copper powder to form a first layer, newly spreading a pure copper powder on the first layer, preheating the pure copper powder and thereafter partially melting the pure copper powder by scanning the pure copper powder with an electron beam, solidifying the pure copper powder to form a second layer, and repeating the foregoing process to add layers. The pure copper powder is a pure copper powder with a Si coating formed thereon, and the preheating temperature is set to be 400° C. or higher and less than 800° C.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: January 16, 2024
    Assignee: JX METALS CORPORATION
    Inventors: Hirofumi Watanabe, Hiroyoshi Yamamoto, Yoshitaka Shibuya, Kenji Sato, Satoru Morioka, Akihiko Chiba, Kenta Aoyagi
  • Patent number: 11810620
    Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 7, 2023
    Assignee: Kioxia Corporation
    Inventors: Hiroyuki Takenaka, Akihiko Chiba, Teppei Higashitsuji, Kiyofumi Sakurai, Hiroaki Nakasa, Youichi Magome
  • Publication number: 20230175101
    Abstract: A method for producing a TiAl alloy member includes a molding step (S10) of laminating a solidified body obtained by melting and solidifying or sintering powder of a TiAl alloy by irradiation of the powder with a beam, to mold a laminated body; and a heat treatment step (S12) of heating the laminated body at a setting temperature that is equal to or higher than a temperature at which a phase transformation to an ? phase is initiated, to produce a TiAl alloy member. By the method for producing a TiAl alloy member, the TiAl alloy member can be easily molded with a decrease in high temperature properties suppressed.
    Type: Application
    Filed: May 23, 2019
    Publication date: June 8, 2023
    Applicants: MITSUBISHI HEAVY INDUSTRIES ENGINE & TURBOCHARGER, LTD., TOHOKU UNIVERSITY
    Inventors: Keisuke SHINZAWA, Atsushi TAKITA, Akihiko CHIBA
  • Publication number: 20230143183
    Abstract: An object of the present invention is to provide an additive manufactured object which is free of solidification cracking due to, e.g., heat shrinkage during additive manufacturing of an aluminum alloy; which is free of anisotropy in strength, and has high strength and ductility. An aluminum alloy powder for additive manufacturing includes aluminum alloy particles in which not less than 0.01% by mass and not more than 1% by mass of a grain refiner is trapped. This grain refiner is at least one selected from the borides and carbides of group 4 elements.
    Type: Application
    Filed: March 22, 2021
    Publication date: May 11, 2023
    Inventors: Yoshiki HASHIZUME, Isao MURAKAMI, Kenta ISHIGAMI, Sotaro AKIYAMA, Akihiko CHIBA, Kenta AOYAGI
  • Patent number: 11626394
    Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 11, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Akihiko Chiba, Takahiro Tsurudo, Kenichi Matoba, Yoshifumi Shimamura, Hiroaki Nakasa, Hiroyuki Takenaka
  • Publication number: 20220246196
    Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.
    Type: Application
    Filed: August 26, 2021
    Publication date: August 4, 2022
    Inventors: Hiroyuki TAKENAKA, Akihiko CHIBA, Teppei HIGASHITSUJI, Kiyofumi SAKURAI, Hiroaki NAKASA, Youichi MAGOME
  • Publication number: 20220226900
    Abstract: Provided is a laminated body molding method for molding a laminated body by irradiating powder fed onto a stage with a beam and thereby fusing and solidifying the powder or sintering the powder. The laminated body molding method includes: a moving distance setting step S22 of setting a moving distance of the stage to a length that is a certain proportion of a particle diameter of the powder; and a molding step S24 of molding the laminated body by repeating a process of moving the stage downward by the moving distance, feeding the powder onto the stage thus moved, and irradiating the fed powder with the beam to fuse and solidify the powder or sinter the powder. With this laminated body molding method, impairment of capabilities of the laminated body can be prevented.
    Type: Application
    Filed: May 23, 2019
    Publication date: July 21, 2022
    Applicants: MITSUBISHI HEAVY INDUSTRIES ENGINE & TURBOCHARGER, LTD., TOHOKU UNIVERSITY
    Inventors: Keisuke SHINZAWA, Atsushi TAKITA, Akihiko CHIBA
  • Publication number: 20220127698
    Abstract: A titanium alloy additive manufacturing product contains 5.50 to 6.75 wt % of Al, 3.50 to 4.50 wt % of V, 0.20 wt % or less of 0, 0.40 wt % or less of Fe, 0.015 wt % or less of H, 0.08 wt % or less of C, 0.05 wt % or less of N, and inevitable impurities, in which a pore content is 0.05 number/mm2 or less, and a tensile strength is 855 MPa or more.
    Type: Application
    Filed: January 31, 2020
    Publication date: April 28, 2022
    Applicants: TOHOKU UNIVERSITY, JAMPT CORPORATION
    Inventors: Akihiko CHIBA, Noritaka YASUDA
  • Publication number: 20220077128
    Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.
    Type: Application
    Filed: February 25, 2021
    Publication date: March 10, 2022
    Applicant: Kioxia Corporation
    Inventors: Akihiko CHIBA, Takahiro TSURUDO, Kenichi MATOBA, Yoshifumi SHIMAMURA, Hiroaki NAKASA, Hiroyuki TAKENAKA
  • Publication number: 20210346954
    Abstract: This invention provides, by simple mechanical treatment, a metal powder that generates no smoke phenomenon when laminating and shaping a metal object even when decreasing a preheating temperature. In the metal powder, a solidification structure including a dendritic structure on the surface of the metal powder has been flattened. The solidification structure including the dendritic structure has been flattened by mechanical treatment including collision treatment of the metal powder. The mechanical treatment is performed by heating the metal powder to 100° C. to 300° C. The metal powder is a metal powder that is heated to a predetermined temperature and whose capacitance component of a measured impedance becomes zero. This metal powder is a powder of a metal alloy produced by an atomization process or a plasma rotation electrode process. The metal alloy includes a nickel-based alloy, a cobalt-chrome alloy, an iron-based alloy, an aluminum alloy, and a titanium alloy.
    Type: Application
    Filed: March 14, 2019
    Publication date: November 11, 2021
    Applicant: TECHNOLOGY RESEARCH ASSOCIATION FOR FUTURE ADDITIVE MANUFACTURING
    Inventors: Akihiko CHIBA, Takahiro KUDO, Youhei DAINO, Kenta AOYAGI
  • Patent number: 11152037
    Abstract: A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: October 19, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroyuki Hara, Hiroyuki Takenaka, Akihiko Chiba
  • Publication number: 20210317541
    Abstract: An iron-based alloy has excellent corrosion resistance and high strength and a method of manufacturing the iron-based alloy. The iron-based alloy includes Cr: 10 to 22 mass %, W: 1 to 12 mass %, and C: 0.1 to 2.3 mass %, with the remainder being unavoidable impurities and Fe, and is composed of a cast material having a structure composed mainly of austenite or a quenched material having a structure composed mainly of martensite and in which carbides are precipitated. The iron-based alloy may further include Cu: 0.5 to 6 mass % and/or Ni: 0.5 to 2.5 mass %, and may further include at least one of Al, Mo, and Si in an amount of 1 to 3 mass %.
    Type: Application
    Filed: September 2, 2019
    Publication date: October 14, 2021
    Applicant: TOHOKU UNIVERSITY
    Inventors: Kenta YAMANAKA, Akihiko CHIBA
  • Patent number: 11141791
    Abstract: An object of the invention is to provide: an alloy article that has excellent homogeneity in the alloy composition and microstructure as well as significant shape controllability, using an HEA with significant mechanical strength and high corrosion resistance; a method for manufacturing the alloy article; and a product using the alloy article. There is provided an alloy article comprising: Co, Cr, Fe, Ni, and Ti elements, each element in content of 5 to 35 atomic %; more than 0 atomic % to 8 atomic % of Mo %; and remainder substances of unavoidable impurities. And, ultrafine particles with an average diameter of 40 nm or less are dispersedly precipitated in matrix phase crystals of the alloy article.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 12, 2021
    Assignee: HITACHI METALS, LTD.
    Inventors: Tadashi Fujieda, Mamoru Hirota, Kosuke Kuwabara, Kinya Aota, Takahiko Kato, Akihiko Chiba, Yuichiro Koizumi, Kenta Yamanaka, Seiichi Watanabe
  • Publication number: 20210299754
    Abstract: A general-purpose process window is constructed while saving cost and time. A process window generation method comprises performing laminating and shaping of samples using sets of at least two parameters for controlling laminating and shaping, which are scattered in a process window, determining, in a process map generated by mapping evaluation results obtained by evaluating the laminated and shaped samples, a boundary of the evaluation results by machine learning; and repeating the performing laminating and shaping and the determining while using a boundary region including the determined boundary as a new process window, and generating a process window separated by a finally determined boundary as a process window that guarantees quality of laminating and shaping.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 30, 2021
    Applicant: TECHNOLOGY RESEARCH ASSOCIATION FOR FUTURE ADDITIVE MANUFACTURING
    Inventors: Kenta AOYAGI, Akihiko CHIBA
  • Patent number: 11100988
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Tsuneo Inaba, Hiroyuki Takenaka, Akihiko Chiba
  • Publication number: 20210174870
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.
    Type: Application
    Filed: September 9, 2020
    Publication date: June 10, 2021
    Applicant: Kioxia Corporation
    Inventors: Tsuneo INABA, Hiroyuki TAKENAKA, Akihiko CHIBA
  • Publication number: 20210083182
    Abstract: A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.
    Type: Application
    Filed: February 27, 2020
    Publication date: March 18, 2021
    Inventors: Hiroyuki HARA, Hiroyuki TAKENAKA, Akihiko CHIBA
  • Publication number: 20210039192
    Abstract: A production method of an additive manufactured object according to an EB-based additive manufacturing method of spreading a pure copper powder, preheating the pure copper powder and thereafter partially melting the pure copper powder by scanning the pure copper powder with an electron beam, solidifying the pure copper powder to form a first layer, newly spreading a pure copper powder on the first layer, preheating the pure copper powder and thereafter partially melting the pure copper powder by scanning the pure copper powder with an electron beam, solidifying the pure copper powder to form a second layer, and repeating the foregoing process to add layers, wherein used as the pure copper powder is a pure copper powder with a Si coating formed thereon, and wherein the preheating temperature is set to be 400° C. or higher and less than 800° C.
    Type: Application
    Filed: December 26, 2019
    Publication date: February 11, 2021
    Inventors: Hirofumi Watanabe, Hiroyoshi Yamamoto, Yoshitaka Shibuya, Kenji Sato, Satoru Morioka, Akihiko Chiba, Kenta Aoyagi