Abstract: An n-type semiconductor layer has a single-crystal structure and is made of a wide-gap semiconducting material. A p-type semiconductor layer is provided on the n-type semiconductor layer and made of a material different from the aforementioned wide-gap semiconducting material, and has either a microcrystalline structure or an amorphous structure. An electrode is provided on at least one of the n-type semiconductor layer and the p-type semiconductor layer.

Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.

Abstract: An object is to provide a technique that can suppress the surge voltage at turn-off without increasing the thickness of a semiconductor device such as an IGBT. A semiconductor device includes first to fourth semiconductor layers stacked in order of the first to fourth semiconductor layers, each having a first conductivity type, and also includes a base layer, an emitter layer, a gate electrode, a collector layer, and a collector electrode. The second semiconductor layer has the lowest impurity concentration of the first conductivity type among the first to fourth semiconductor layers, and the impurity concentration of the first conductivity type of the third semiconductor layer is higher than the impurity concentration of the first conductivity type of the fourth semiconductor layer.

Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.

Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.

Abstract: An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer.

Abstract: Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Alx1Iny1Ga1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Alx2Iny2Ga1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.

Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.

Abstract: A power semiconductor device includes an emitter electrode disposed on a semiconductor substrate and through which a main current flows, a conductive layer that is disposed on the emitter electrode and is not a sintered compact, and a sintered metal layer that is disposed on the conductive layer and is a sintered compact. The sintered metal layer has a size to cover all the emitter electrode in plan view, and has higher heat conductivity than the conductive layer. The power semiconductor device can improve heat dissipation performance and adhesion.

Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.

Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.

Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.

Abstract: A power semiconductor device includes an emitter electrode disposed on a semiconductor substrate and through which a main current flows, a conductive layer that is disposed on the emitter electrode and is not a sintered compact, and a sintered metal layer that is disposed on the conductive layer and is a sintered compact. The sintered metal layer has a size to cover all the emitter electrode in plan view, and has higher heat conductivity than the conductive layer. The power semiconductor device can improve heat dissipation performance and adhesion.

Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.

Abstract: A semiconductor apparatus includes: a p-type base layer provided on a top surface side of an n-type drift layer; an n-type emitter layer provided on a top surface side of the p-type base layer; a first control electrode having a trench gate electrode embedded so as to reach from a surface layer of the n-type emitter layer to the n-type drift layer; a second control electrode having a trench gate electrode embedded so as to reach from the p-type base layer to the n-type drift layer; a p-type collector layer provided on a bottom surface side of the n-type drift layer; and a diode whose anode side and cathode side are connected to the first control electrode and the second control electrodes, respectively. It is possible to improve the controllability of dV/dt by a gate resistor.

Abstract: In a pressure contact type semiconductor apparatus, a second intermediate electrode on a second semiconductor chip has one or more second through holes. The one or more second through holes are fluidly separated from a space hermetically sealed by a cylindrical body, a first common electrode plate and a second common electrode plate. The pressure contact type semiconductor apparatus thereby has high reliability.

Abstract: In a pressure contact type semiconductor apparatus, a second intermediate electrode on a second semiconductor chip has one or more second through holes. The one or more second through holes are fluidly separated from a space hermetically sealed by a cylindrical body, a first common electrode plate and a second common electrode plate. The pressure contact type semiconductor apparatus thereby has high reliability.

Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.

Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.

Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.