Patents by Inventor Akihiko Osawa
Akihiko Osawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170044686Abstract: A semiconductor manufacturing apparatus includes a chamber, a reaction-gas inlet, a gas exhaust port, a rotation unit, a semiconductor wafer holder, a heater, and a purge-gas inlet. The wafer holder includes a first hold region to hold the semiconductor wafer and a second hold region held by the rotation unit. The second hold region surrounds the first hold region. The level of the first hold region and the level of the second hold region differ. A plurality of ventholes is provided to the first hold region so that the ventholes are just below a sidewall of the semiconductor wafer held by the first hold region.Type: ApplicationFiled: October 26, 2016Publication date: February 16, 2017Inventors: Shinya Higashi, Shinya Sato, Tomoyuki Sakuma, Akihiko Osawa, Hiroaki Kobayashi, Osamu Yamazaki, Hiroshi Nishimura
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Publication number: 20140283748Abstract: A semiconductor manufacturing apparatus includes a chamber, a reaction-gas inlet, a gas exhaust port, a rotation unit, a semiconductor wafer holder, a heater, and a purge-gas inlet. The wafer holder includes a first hold region to hold the semiconductor wafer and a second hold region held by the rotation unit. The second hold region surrounds the first hold region. The level of the first hold region and the level of the second hold region differ. A plurality of ventholes is provided to the first hold region so that the ventholes are just below a sidewall of the semiconductor wafer held by the first hold region.Type: ApplicationFiled: September 11, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinya Higashi, Shinya Sato, Tomoyuki Sakuma, Akihiko Osawa, Hiroaki Kobayashi, Osamu Yamazaki, Hiroshi Nishimura
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Patent number: 7227223Abstract: A semiconductor device, and particularly an MOS transistor device, wherein in order to increase a channel region density and to achieve a low resistance of a transistor device there is provided a first gate electrode group having a plurality of gate electrodes formed on a semiconductor substrate to be away from each other at first equal spacings, a second gate electrode group having a plurality of gate electrodes formed on the semiconductor substrate to be away from each other at the first equal spacings, a source contact portion formed away from the first or the second gate electrode group at a second spacing, and source regions for electrically interconnecting the first gate electrode group and the source contact. The source regions are connected to each other at one end of the first gate electrode group, and separated at the other end of the first gate electrode group. In addition, the gate electrodes of the first group are connected each other at the other end.Type: GrantFiled: July 15, 2003Date of Patent: June 5, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Noboru Matsuda, Hitoshi Kobayashi, Masaru Kawakatsu, Akihiko Osawa
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Publication number: 20060145290Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.Type: ApplicationFiled: December 6, 2005Publication date: July 6, 2006Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Wataru Saito, Masakazu Yamaguchi, Ichiro Omura
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Patent number: 6995426Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.Type: GrantFiled: December 26, 2002Date of Patent: February 7, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Wataru Saito, Masakazu Yamaguchi, Ichiro Omura
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Patent number: 6740931Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.Type: GrantFiled: April 17, 2003Date of Patent: May 25, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kouzuki, Hideki Okumura, Hitoshi Kobayashi, Satoshi Aida, Masaru Izumisawa, Akihiko Osawa
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Publication number: 20040016962Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.Type: ApplicationFiled: April 24, 2003Publication date: January 29, 2004Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Publication number: 20040012038Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.Type: ApplicationFiled: April 17, 2003Publication date: January 22, 2004Inventors: Shigeo Kouzuki, Hideki Okumura, Hitoshi Kobayashi, Satoshi Aida, Masaru Izumisawa, Akihiko Osawa
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Publication number: 20040012051Abstract: A semiconductor device, and particularly an MOS transistor device, wherein in order to increase a channel region density and to achieve a low resistance of a transistor device there is provided a first gate electrode group having a plurality of gate electrodes formed on a semiconductor substrate to be away from each other at first equal spacings, a second gate electrode group having a plurality of gate electrodes formed on the semiconductor substrate to be away from each other at the first equal spacings, a source contact portion formed away from the first or the second gate electrode group at a second spacing, and source regions for electrically interconnecting the first gate electrode group and the source contact. The source regions are connected to each other at one end of the first gate electrode group, and separated at the other end of the first gate electrode group. In addition, the gate electrodes of the first group are connected each other at the other end.Type: ApplicationFiled: July 15, 2003Publication date: January 22, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Noboru Matsuda, Hitoshi Kobayashi, Masaru Kawakatsu, Akihiko Osawa
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Patent number: 6627499Abstract: Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depletion layer is extended toward the base region so as to improve the breakdown voltage. The impurity diffusion region is formed by forming a trench in a part of the base region, a conductive film being buried in the trench, followed by introducing by ion implantation an impurity of the conductivity type equal to that in the base region into the side wall and the bottom of the trench in a concentration lower than that in the base region and subsequently diffusing the implanted impurity ions. The impurity diffusion region thus formed permits relaxing the electric field concentration on the corner portion of the gate trench and on the extended portion of the base region so as to improve the breakdown voltage.Type: GrantFiled: November 27, 2002Date of Patent: September 30, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Akihiko Osawa
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Publication number: 20030122222Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.Type: ApplicationFiled: December 26, 2002Publication date: July 3, 2003Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Wataru Saito, Masakazu Yamaguchi, Ichiro Omura
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Publication number: 20030075760Abstract: Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depletion layer is extended toward the base region so as to improve the breakdown voltage. The impurity diffusion region is formed by forming a trench in a part of the base region, a conductive film being buried in the trench, followed by introducing by ion implantation an impurity of the conductivity type equal to that in the base region into the side wall and the bottom of the trench in a concentration lower than that in the base region and subsequently diffusing the implanted impurity ions. The impurity diffusion region thus formed permits relaxing the electric field concentration on the corner portion of the gate trench and on the extended portion of the base region so as to improve the breakdown voltage.Type: ApplicationFiled: November 27, 2002Publication date: April 24, 2003Inventor: Akihiko Osawa
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Patent number: 6501129Abstract: Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depletion layer is extended toward the base region so as to improve the breakdown voltage. The impurity diffusion region is formed by forming a trench in a part of the base region, a conductive film being buried in the trench, followed by introducing by ion implantation an impurity of the conductivity type equal to that in the base region into the side wall and the bottom of the trench in a concentration lower than that in the base region and subsequently diffusing the implanted impurity ions. The impurity diffusion region thus formed permits relaxing the electric field concentration on the corner portion of the gate trench and on the extended portion of the base region so as to improve the breakdown voltage.Type: GrantFiled: March 29, 2001Date of Patent: December 31, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Akihiko Osawa
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Publication number: 20020130359Abstract: A semiconductor device comprises a drain region formed on the reverse side of a semiconductor substrate, a base region formed on the drain region and having parts partially exposed at plural positions on a principal plane of the substrate, a source region which has one plane in contact with the base region and the other plane exposed on the principal plane of the substrate, a gate insulating film formed only on a wall of a trench, which is formed in the substrate to reach the drain region, a gate electrode formed so as to be embedded in the trench and a top surface thereof is situated above the junction plane of the source and base regions and at a position lower than the principal plane of the substrate, and an insulating film embedded above the gate electrode in the trench.Type: ApplicationFiled: March 14, 2002Publication date: September 19, 2002Inventors: Hideki Okumura, Akihiko Osawa, Takayoshi Ino
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Publication number: 20010025984Abstract: Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depletion layer is extended toward the base region so as to improve the breakdown voltage. The impurity diffusion region is formed by forming a trench in a part of the base region, a conductive film being buried in the trench, followed by introducing by ion implantation an impurity of the conductivity type equal to that in the base region into the side wall and the bottom of the trench in a concentration lower than that in the base region and subsequently diffusing the implanted impurity ions. The impurity diffusion region thus formed permits relaxing the electric field concentration on the corner portion of the gate trench and on the extended portion of the base region so as to improve the breakdown voltage.Type: ApplicationFiled: March 29, 2001Publication date: October 4, 2001Inventor: Akihiko Osawa
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Patent number: 6239464Abstract: A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.Type: GrantFiled: January 7, 1999Date of Patent: May 29, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Masanobu Tsuchitani, Keita Suzuki, Akihiko Osawa, Yoshiro Baba
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Patent number: 6084263Abstract: The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example, a semiconductive film is formed on the surface of an n-type Si substrate between a second p-type base layer selectively formed on the surface of the Si substrate and a channel stop layer formed to surround the second p-type base layer at a predetermined interval. The dangling bond density of the semiconductive film is set at 1.25.times.1018 cm.sup.-3. With this structure, the discrete level in the band gap approach a continuum, and the time required to populate the trapping level in the semiconductive film with carriers is shortened.Type: GrantFiled: February 23, 1998Date of Patent: July 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masanobu Tsuchitani, Shizue Hori, Akihiko Osawa
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Patent number: 6060747Abstract: A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.Type: GrantFiled: September 23, 1998Date of Patent: May 9, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Akihiko Osawa, Yoshiro Baba, Noboru Matsuda, Masanobu Tsuchitani
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Patent number: 6031276Abstract: A semiconductor device includes a plurality of defect layers separated from one another in the semiconductor layer. A distance separating any adjacent ones of the defect layers is kept such that they are prevented from contacting each other and those regions having effect of shortening a carrier lifetime overlap each other.Type: GrantFiled: October 15, 1997Date of Patent: February 29, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Akihiko Osawa, Yoshiro Baba, Masanobu Tsuchitani, Shizue Hori
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Patent number: 6010950Abstract: The most distinctive feature of the present invention lies in that a warp and crystal defects can be prevented from occurring and a processing margin for forming an isolation groove can be improved in an intelligent power device including a power element section and an IC control section within one chip. A bonded wafer is obtained by bonding an active-layer substrate and a supporting substrate with an epitaxially grown silicon layer interposed therebetween so as to cover an oxide film selectively formed at the interface of the active-layer substrate. Isolation trenches are then formed in the bonded wafer to such a depth as to reach the oxide film from the element forming surface of the active-layer substrate. Thus, an IC controller is formed within a dielectric isolation region surrounded with the isolation trenches and the oxide film and accordingly the IC controller can effectively be isolated by a dielectric.Type: GrantFiled: February 19, 1998Date of Patent: January 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Akihiko Osawa, Yoshiro Baba