Patents by Inventor Akihiko Sugai

Akihiko Sugai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210119008
    Abstract: A semiconductor device has: a semiconductor substrate; a drift layer of a first conductivity type; a well region of a second conductivity type; a high-concentration region of the second conductivity type, a source region of the first conductivity type; an insulating film provided on the drift layer; a first contact metal film in contact with the source region and the high-concentration region through a first opening provided in the insulating film; and a second contact metal film formed on a surface of the first contact metal film and contacting the high-concentration region through a second opening provided in the first contact metal film; a source electrode film formed on a surface of a contact metal layer including the first contact metal film and the second contact metal film. The first contact metal film includes titanium nitride, and the second contact metal film includes titanium.
    Type: Application
    Filed: April 11, 2018
    Publication date: April 22, 2021
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Teppei TAKAHASHI, Tetsuto INOUE, Akihiko SUGAI, Takashi MOCHIZUKI, Shunichi NAKAMURA
  • Patent number: 10600869
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 24, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Shunichi Nakamura, Akihiko Sugai, Tetsuto Inoue
  • Patent number: 10510841
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 17, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Shunichi Nakamura, Akihiko Sugai, Tetsuto Inoue
  • Publication number: 20190252498
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Inventors: Shunichi NAKAMURA, Akihiko SUGAI, Tetsuto INOUE
  • Patent number: 9831316
    Abstract: A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: November 28, 2017
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
  • Publication number: 20170229541
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Application
    Filed: September 18, 2015
    Publication date: August 10, 2017
    Inventors: Shunichi NAKAMURA, Akihiko SUGAI, Tetsuto INOUE
  • Patent number: 9716168
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 25, 2017
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
  • Patent number: 9640618
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a greater depth than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds only a part of the gate trench 20 in the horizontal direction is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad 89 is disposed is a gate region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 2, 2017
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
  • Publication number: 20170040423
    Abstract: A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.
    Type: Application
    Filed: July 10, 2015
    Publication date: February 9, 2017
    Applicant: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA
  • Publication number: 20160293753
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.
    Type: Application
    Filed: September 24, 2014
    Publication date: October 6, 2016
    Applicant: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA
  • Publication number: 20160254356
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a greater depth than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds only a part of the gate trench 20 in the horizontal direction is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad 89 is disposed is a gate region.
    Type: Application
    Filed: September 24, 2014
    Publication date: September 1, 2016
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA
  • Patent number: 8637872
    Abstract: A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate (1) having a first conduction type made of SiC, a PN junction region (7a) and a Schottky junction region (7b) are provided, in the PN junction region (7a), a convex portion (2a) which has a trapezoidal shape in sectional view and includes a second conduction type layer (2) provided on the semiconductor substrate (1) and a contact layer (3) which is in ohmic contact with the second conduction type layer (2) of the convex portion (2a) are provided, and Schottky electrode (4) covers the side surface of the convex portion (2a) and the contact layer (3), and is provided continuously over the PN junction region (7a) and the Schottky junction region (7b).
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: January 28, 2014
    Assignee: Showa Denko K.K.
    Inventor: Akihiko Sugai
  • Patent number: 8513674
    Abstract: A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 20, 2013
    Assignee: Showa Denko K.K.
    Inventors: Akihiko Sugai, Yasuyuki Sakaguchi
  • Publication number: 20110233563
    Abstract: A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).
    Type: Application
    Filed: November 25, 2009
    Publication date: September 29, 2011
    Applicant: SHOWA DENKO K.K.
    Inventors: Akihiko Sugai, Yasuyuki Sakaguchi
  • Publication number: 20110220918
    Abstract: A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate (1) having a first conduction type made of SiC, a PN junction region (7a) and a Schottky junction region (7b) are provided, in the PN junction region (7a), a convex portion (2a) which has a trapezoidal shape in sectional view and includes a second conduction type layer (2) provided on the semiconductor substrate (1) and a contact layer (3) which is in ohmic contact with the second conduction type layer (2) of the convex portion (2a) are provided, and Schottky electrode (4) covers the side surface of the convex portion (2a) and the contact layer (3), and is provided continuously over the PN junction region (7a) and the Schottky junction region (7b).
    Type: Application
    Filed: October 23, 2009
    Publication date: September 15, 2011
    Applicant: SHOWA DENKO K.K.
    Inventor: Akihiko Sugai
  • Patent number: 7855413
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 21, 2010
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
  • Publication number: 20070194364
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Application
    Filed: April 20, 2007
    Publication date: August 23, 2007
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
  • Patent number: 7230298
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: June 12, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
  • Publication number: 20030042555
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Application
    Filed: July 18, 2002
    Publication date: March 6, 2003
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai