Patents by Inventor Akihiro Itou

Akihiro Itou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200381304
    Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.
    Type: Application
    Filed: May 22, 2020
    Publication date: December 3, 2020
    Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Publication number: 20200294791
    Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 17, 2020
    Inventors: Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Patent number: 10714356
    Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: July 14, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou, Noriyuki Matsubara
  • Publication number: 20200098636
    Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 26, 2020
    Inventors: Atsushi HARIKAI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI, Akihiro ITOU
  • Publication number: 20200002850
    Abstract: A first aspect of the present invention is carbon fiber wherein the surface of a monofilament has a center line average roughness Ra of 6.0 nm or more and 13 nm or less, and the monofilament has a long diameter/short diameter ratio of 1.11 or more and 1.245 or less. A second aspect of the present invention is carbon fiber precursor acrylic fiber wherein the surface of a monofilament has a center line average roughness Ra of 18 nm or more and 27 nm or less, and the monofilament has a long diameter/short diameter ratio of 1.11 or more and 1.245 or less. The carbon fiber according to the first aspect is obtained by stabilizing and carbonizing under specific conditions the carbon fiber precursor acrylic fiber according to the second aspect.
    Type: Application
    Filed: August 15, 2019
    Publication date: January 2, 2020
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Naomasa Matsuyama, Yuutarou Nakamura, Norifumi Hirota, Hiroko Matsumura, Katsuhiko Ikeda, Kouki Wakabayashi, Tadashi Ootani, Akihiro Itou, Kenji Hirano, Akito Hatayama, Kenji Kaneta, Atsushi Nakajima
  • Patent number: 10497622
    Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: December 3, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Mitsuru Hiroshima, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou
  • Publication number: 20190221479
    Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 18, 2019
    Inventors: Shogo OKITA, Atsushi HARIKAI, Noriyuki MATSUBARA, Hidefumi SAEKI, Akihiro ITOU
  • Publication number: 20190221324
    Abstract: Provided is a neutron shielding material having excellent transparency and high neutron shielding ability. In this neutron shielding material, light transmittance at wave length of 400 to 700 nm is 80% or greater, and the thickness of a 1/10 divalent layer of a neutron generated from Californium 252 is 14 cm or less.
    Type: Application
    Filed: June 6, 2017
    Publication date: July 18, 2019
    Inventors: Yuusuke WATANABE, Akihiro ITOU, Takaya SHINMURA, Teruo HASHIMOTO, Takaaki KISHIMOTO
  • Patent number: 10297487
    Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou
  • Patent number: 10297489
    Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: May 21, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 10276423
    Abstract: A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to cover each of the element regions and to expose the dividing region; exposing the front surface to plasma in a state where a back surface of the semiconductor wafer is held with a dicing tape to dice the semiconductor wafer into a plurality of semiconductor chips by etching the dividing region exposed from the mask up to the back surface while protecting each of the element regions with the mask from plasma; and removing the mask from the front surface together with an adhesive tape by peeling off the adhesive tape after sticking the adhesive tape to the side of the front surface.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 30, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Koji Tamura, Akihiro Itou, Atsushi Harikai, Noriyuki Matsubara
  • Publication number: 20190122892
    Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 25, 2019
    Inventors: Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU, Noriyuki MATSUBARA
  • Patent number: 10242914
    Abstract: A semiconductor chip manufacturing method includes forming a mask on a surface of a semiconductor wafer, forming an opening on the mask, exposing a dividing region of the semiconductor wafer, a rear surface of the semiconductor wafer is held by a dicing tape via an adhesive layer, singulating the semiconductor wafer into a plurality of semiconductor chips by etching the semiconductor wafer exposed to the opening with a first plasma until the semiconductor wafer reaches a rear surface, removing the mask so that the plurality of element chips from which the mask is removed are held by the holding sheet via the adhesive layer. At the time of removing the mask, the mask is removed from an alkaline developer having a dissolution rate of the mask larger than a dissolution rate of the adhesive layer.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 26, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Noriyuki Matsubara, Atsushi Harikai, Akihiro Itou
  • Patent number: 10236266
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou, Katsumi Takano, Mitsuru Hiroshima
  • Publication number: 20180342424
    Abstract: A semiconductor chip manufacturing method includes forming a mask on a surface of a semiconductor wafer, forming an opening on the mask, exposing a dividing region of the semiconductor wafer, a rear surface of the semiconductor wafer is held by a dicing tape via an adhesive layer, singulating the semiconductor wafer into a plurality of semiconductor chips by etching the semiconductor wafer exposed to the opening with a first plasma until the semiconductor wafer reaches a rear surface, removing the mask so that the plurality of element chips from which the mask is removed are held by the holding sheet via the adhesive layer. At the time of removing the mask, the mask is removed from an alkaline developer having a dissolution rate of the mask larger than a dissolution rate of the adhesive layer.
    Type: Application
    Filed: April 13, 2018
    Publication date: November 29, 2018
    Inventors: SHOGO OKITA, NORIYUKI MATSUBARA, ATSUSHI HARIKAI, AKIHIRO ITOU
  • Publication number: 20180240678
    Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 23, 2018
    Inventors: Akihiro ITOU, Atsushi HARIKAI, Noriyuki MATSUBARA, Shogo OKITA
  • Publication number: 20180233395
    Abstract: A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to cover each of the element regions and to expose the dividing region; exposing the front surface to plasma in a state where a back surface of the semiconductor wafer is held with a dicing tape to dice the semiconductor wafer into a plurality of semiconductor chips by etching the dividing region exposed from the mask up to the back surface while protecting each of the element regions with the mask from plasma; and removing the mask from the front surface together with an adhesive tape by peeling off the adhesive tape after sticking the adhesive tape to the side of the front surface.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 16, 2018
    Inventors: Shogo OKITA, Koji TAMURA, Akihiro ITOU, Atsushi HARIKAI, Noriyuki MATSUBARA
  • Patent number: 10049933
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 14, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou, Katsumi Takano, Mitsuru Hiroshima
  • Publication number: 20180158713
    Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.
    Type: Application
    Filed: November 27, 2017
    Publication date: June 7, 2018
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI, NORIYUKI MATSUBARA, AKIHIRO ITOU
  • Patent number: 9896771
    Abstract: An exemplary dehydrogenation device for generating a hydrogen gas through dehydrogenation according to the present disclosure comprises an anode containing a dehydrogenation catalyst, a cathode containing catalyst capable of reducing protons, and a proton conductor disposed between the anode and the cathode. The proton conductor has a perovskite crystal structure expressed by the compositional formula AaB1-xB?xO3-?. The A element is an alkaline-earth metal and is contained in a range of 0.4<a<0.9, where the a value represents a mole fraction of this element, and the B? element is a trivalent group 3 or group 13 element and is contained in a range of 0.2<x<0.6, where the x value represents a mole fraction of this element.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 20, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuji Zenitani, Takashi Nishihara, Tetsuya Asano, Akihiro Itou, Hiroki Takeuchi