Abstract: A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first well region of a second conductivity-type provided in the semiconductor base body; at least one second well region of the first conductivity-type implementing a part of a high-side circuit provided in the first well region; a buried layer of the second conductivity-type provided at a bottom of the first well region and having a higher impurity concentration than the first well region; a voltage blocking region of the second conductivity-type provided at a circumference of the first well region; and an extraction region of the first conductivity-type provided to have a greater depth than the second well region at least at a part of a circumference of the high-side circuit in the first well region so as to be opposed to the second well region.

Abstract: A semiconductor device includes: a pad; a control circuit; a plurality of high-potential-side circuit regions having distances to the pad different from each other, each including a gate drive circuit, a SET-side level shifter, a RESET-side level shifter, and a circular wire; a SET-side wire electrically connects the pad with the SET-side level shifters; and a RESET-side wire electrically connects the pad with the RESET-side level shifters, wherein the circular wire located closer to the pad is electrically connected to the SET-side wire and the RESET-side wire via the circular wire 8u located further from the pad.

Abstract: A semiconductor device includes: a pad; a control circuit; a plurality of high-potential-side circuit regions having distances to the pad different from each other, each including a gate drive circuit, a SET-side level shifter, a RESET-side level shifter, and a circular wire; a SET-side wire electrically connects the pad with the SET-side level shifters; and a RESET-side wire electrically connects the pad with the RESET-side level shifters, wherein the circular wire located closer to the pad is electrically connected to the SET-side wire and the RESET-side wire via the circular wire 8u located further from the pad.

Abstract: A semiconductor device includes an n type first semiconductor region in which a first parasitic diode is formed with a p type semiconductor substrate; an n type second semiconductor region in which a second parasitic diode is formed with the p type semiconductor substrate; a control circuit in the second semiconductor region outputting a gate control signal, a gate drive circuit in the second semiconductor region; a level shift circuit that converts the gate control signal to a converted gate control signal and outputs the converted gate control signal to the gate drive circuit; a diode connected to a path of a noise current caused by a negative voltage noise passing through the second parasitic diode, the diode being connected to the path in a direction opposite to a direction in which the noise current would flow; and a capacitor connected to an anode of said diode.

Abstract: Provided is a semiconductor device capable of preventing a malfunction of a high-side gate driver circuit that is caused by a negative voltage surge. A diode is connected between a p-type bulk substrate configuring a semiconductor layer, and a first potential (GND potential), and a signal is transmitted from a control circuit that is formed in an n diffusion region configuring a first semiconductor region through a first level down circuit and a first level up circuit to a high-side gate driver circuit that is formed in an n diffusion region configuring a second semiconductor region. As a result, a malfunction of the high-side gate driver circuit that is caused by a negative voltage surge can be prevented.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer.

Abstract: Provided is a semiconductor device capable of preventing a malfunction of a high-side gate driver circuit that is caused by a negative voltage surge. A diode is connected between a p-type bulk substrate configuring a semiconductor layer, and a first potential (GND potential), and a signal is transmitted from a control circuit that is formed in an n diffusion region configuring a first semiconductor region through a first level down circuit and a first level up circuit to a high-side gate driver circuit that is formed in an n diffusion region configuring a second semiconductor region. As a result, a malfunction of the high-side gate driver circuit that is caused by a negative voltage surge can be prevented.

Abstract: Provided is a semiconductor device capable of preventing a malfunction of a high-side gate driver circuit that is caused by a negative voltage surge. A diode is connected between a p-type bulk substrate configuring a semiconductor layer, and a first potential (GND potential), and a signal is transmitted from a control circuit that is formed in an n diffusion region configuring a first semiconductor region through a first level down circuit and a first level up circuit to a high-side gate driver circuit that is formed in an n diffusion region configuring a second semiconductor region. As a result, a malfunction of the high-side gate driver circuit that is caused by a negative voltage surge can be prevented.

Abstract: A semiconductor device provides reduced size and increased performance, and includes a semiconductor layer having a surface layer including first and second semiconductor regions connected to first and second potentials, respectively; a third semiconductor region provided inside the first semiconductor region and connected to a third potential; a fourth semiconductor region provided inside the second semiconductor region and connected to the third potential; a plurality of a first element provided in each of the first, second, third, and fourth semiconductor regions; a first isolation region provided between and in contact with the first and second semiconductor regions, electrically connected to the semiconductor layer, and connected to a fourth potential; and a second isolation region which encloses the periphery of and maintains a withstand voltage of the first and second semiconductor regions. The third and fourth potentials are lower than the second potential, which is lower than the first potential.

Abstract: A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion.

Abstract: An n? type diffusion region surrounds a high side well region and is electrically isolated from a low side region. In the n? diffusion region formed are a first p type diffusion region and the second p type diffusion region separated with each other. The first p type diffusion region composes a double RESURF structure in an nch MOSFET in the level shift-up circuit, and in a high voltage junction terminating structure. The second p type diffusion region composes a double RESURF structure of a pch MOSFET of a level shift-down circuit. The impurity concentration of the n? type diffusion region is in the range of 1.3×1012/cm2 to 2.8×1012/cm2. The impurity concentration of the first p type diffusion region and the impurity concentration of the second p type diffusion region are in the range of 1.1×1012/cm2 to 1.4×1012/cm2.

Abstract: Provided is a semiconductor device capable of preventing a malfunction of a high-side gate driver circuit that is caused by a negative voltage surge. A diode is connected between a p-type bulk substrate configuring a semiconductor layer, and a first potential (GND potential), and a signal is transmitted from a control circuit that is formed in an n diffusion region configuring a first semiconductor region through a first level down circuit and a first level up circuit to a high-side gate driver circuit that is formed in an n diffusion region configuring a second semiconductor region. As a result, a malfunction of the high-side gate driver circuit that is caused by a negative voltage surge can be prevented.

Abstract: A semiconductor device provides reduced size and increased performance, and includes a semiconductor layer having a surface layer including first and second semiconductor regions connected to first and second potentials, respectively; a third semiconductor region provided inside the first semiconductor region and connected to a third potential; a fourth semiconductor region provided inside the second semiconductor region and connected to the third potential; a plurality of a first element provided in each of the first, second, third, and fourth semiconductor regions; a first isolation region provided between and in contact with the first and second semiconductor regions, electrically connected to the semiconductor layer, and connected to a fourth potential; and a second isolation region which encloses the periphery of and maintains a withstand voltage of the first and second semiconductor regions. The third and fourth potentials are lower than the second potential, which is lower than the first potential.

Abstract: An n? type diffusion region surrounds a high side well region and is electrically isolated from a low side region. In the n? diffusion region formed are a first p type diffusion region and the second p type diffusion region separated with each other. The first p type diffusion region composes a double RESURF structure in an nch MOSFET in the level shift-up circuit, and in a high voltage junction terminating structure. The second p type diffusion region composes a double RESURF structure of a pch MOSFET of a level shift-down circuit. The impurity concentration of the n? type diffusion region is in the range of 1.3×1012/cm2 to 2.8×1012/cm2. The impurity concentration of the first p type diffusion region and the impurity concentration of the second p type diffusion region are in the range of 1.1×1012/cm2 to 1.4×1012/cm2.

Abstract: A polysilicon resistor includes a high resistance conductor, a low resistance conductor adjacent to one end portion of the high resistance conductor, and a low resistance conductor adjacent to the other end portion of the high resistance conductor. Of the high resistance conductor, a width of a first place reacting most actively when a current flows into a polysilicon fuse is narrowest. Of the high resistance conductor, a width of a second place serving as an interface with each of the low resistance conductors is widest. The width of the high resistance conductor increases gradually from the first place toward the second place.

Abstract: A p diffusion region is selectively provided in a surface layer of an n? diffusion region which is provided in the front surface of a p-type bulk substrate. A power supply potential is applied to the n? diffusion region. A PMOS of a high-side driving circuit and a clamping PMOS are arranged in the n? diffusion region. An intermediate potential is applied to the p diffusion region. An NMOS of the high-side driving circuit is arranged in the p diffusion region. The high-side driving circuit operates at a potential between an intermediate potential, which is a reference potential, and the power supply potential. The threshold voltage of the clamping PMOS is in the range of about ?0.1 V to ?0.6 V. A p+ source region and a gate electrode of the clamping PMOS are connected to a VB electrode.

Abstract: A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET.

Abstract: A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion.

Abstract: A semiconductor device is disclosed which has a high voltage isolation structure that is a RESURF structure, wherein it is possible to reduce a displacement current generated by dV/dt noise, and a method of manufacturing the semiconductor device. It is possible to increase a lateral resistance without changing the total amount of electric charges in the uppermost surface p-type diffusion layer by using an uppermost surface p-type diffusion layer configuring a double-RESURF structure being formed so that high concentration regions with a deep diffusion depth and low concentration regions with a shallow diffusion depth are alternately arranged adjacent to each other. As a result, it is possible to reduce a displacement current generated by dV/dt noise.