Abstract: A display device includes a first data driver which is disposed at an upper side of a display panel and supplies a data signal to data lines of a plurality of data lines, a second data driver which is disposed at a lower side of the display panel and supplies a data signal to remaining data lines of the plurality of data lines, and a signal controller which outputs a corrected image signal, based on a first lookup table which stores a correction value of a first input image signal for the first data driver and a second lookup table which stores a correction value of a second input image signal for the second data driver.

Abstract: A display device includes a backlight unit including a plurality of light emitting blocks, a first controller configured to generate first block representative value information for first pixel blocks based on first image data, and a second controller configured to generate second block representative value information for second pixel blocks based on second image data. The first controller receives the second block representative value information from the second controller, and the second controller receives the first block representative value information from the first controller. The first and second controllers generate duty information for the plurality of light emitting blocks based on the first and second block representative value information, and generate light profile information of the backlight unit. The first controller compensates the first image data based on the light profile information, and the second controller compensates the second image data based on the light profile information.

Abstract: A display device includes a backlight unit including a plurality of light emitting blocks, a first controller configured to generate first block representative value information for first pixel blocks based on first image data, and a second controller configured to generate second block representative value information for second pixel blocks based on second image data. The first controller receives the second block representative value information from the second controller, and the second controller receives the first block representative value information from the first controller. The first and second controllers generate duty information for the plurality of light emitting blocks based on the first and second block representative value information, and generate light profile information of the backlight unit. The first controller compensates the first image data based on the light profile information, and the second controller compensates the second image data based on the light profile information.

Abstract: A display device includes a first data driver which is disposed at an upper side of a display panel and supplies a data signal to data lines of a plurality of data lines, a second data driver which is disposed at a lower side of the display panel and supplies a data signal to remaining data lines of the plurality of data lines, and a signal controller which outputs a corrected image signal, based on a first lookup table which stores a correction value of a first input image signal for the first data driver and a second lookup table which stores a correction value of a second input image signal for the second data driver.

Abstract: A method of driving a transparent liquid crystal display apparatus includes a transparent display panel including a brightness sensor and a timing controller. The timing controller includes a YCbCr converter configured to convert input pixel data to YCbCr data, a histogram extractor configured to receive the YCbCr data and generate histogram information about the number of values corresponding to each of brightness data, a grayscale analysis unit configured to analyze the histogram information and determine a type of an input image, an image processer configured to process the YCbCr data according to the type of the input image and the ambient brightness information and generate an output YCbCr? data, and an RGB converter configured to convert the output YCbCr? data to output image data.

Abstract: A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

Abstract: A display apparatus including a classifier configured to classify image data into preset data of an n-bits (“n” is a natural number), a toggle counter configured to count a number of toggles based on preset data of a present horizontal line and a previous horizontal line and to calculate a final toggle number using a weighted values corresponding to a swing width between data voltages of the present and previous horizontal lines, a determiner configured to determine a representative toggle number of a present frame based on a plurality of final toggle numbers of the present frame, compare the representative toggle number with a plurality of threshold values and determine a level of a power control signal based on a compared result.

Abstract: A method of driving a transparent liquid crystal display apparatus includes a transparent display panel including a brightness sensor and a timing controller. The timing controller includes a YCbCr converter configured to convert input pixel data to YCbCr data, a histogram extractor configured to receive the YCbCr data and generate histogram information about the number of values corresponding to each of brightness data, a grayscale analysis unit configured to analyze the histogram information and determine a type of an input image, an image processer configured to process the YCbCr data according to the type of the input image and the ambient brightness information and generate an output YCbCr? data, and an RGB converter configured to convert the output YCbCr? data to output image data.

Abstract: An I2C router system includes an I2C router part, a first slave device and a second slave device. The I2C router part includes a first I2C router configured to output a first I2C signal via a first I2C bus, and a second I2C router configured to output a second I2C signal via a second I2C bus. The first slave device can be configured to receive the first I2C signal via the first I2C bus. The second slave device can be configured to receive the second I2C signal via the second I2C bus.

Abstract: A display apparatus including a classifier configured to classify image data into preset data of an n-bits (“n” is a natural number), a toggle counter configured to count a number of toggles based on preset data of a present horizontal line and a previous horizontal line and to calculate a final toggle number using a weighted values corresponding to a swing width between data voltages of the present and previous horizontal lines, a determiner configured to determine a representative toggle number of a present frame based on a plurality of final toggle numbers of the present frame, compare the representative toggle number with a plurality of threshold values and determine a level of a power control signal based on a compared result.

Abstract: A display apparatus includes a plurality of pixels connected to a plurality of gate lines and a plurality of data lines and a timing controller, in which each pixel includes a first sub-pixel and a second sub-pixel. In such a display apparatus, the timing controller provides the first sub-pixel and the second sub-pixel with a first data signal and a second data signal corresponding to one of a high gray scale curve and a low gray scale curve, alternately every frame, when the image signal is a first type of image signal, and the timing controller provides the first sub-pixel with a first data signal corresponding to the high gray scale curve and the second sub-pixel with a second data signal corresponding to the low gray scale curve when the image signal is a first type of image signal.

Abstract: A liquid crystal display includes a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a plurality of pixels. The timing controller receives an image data, compares a previous line data with a present line data to determine whether the present line data needs to be compensated, and generates a first modulation line data. In addition, the timing controller calculates the first modulation data and a delay compensation value to generate a second modulation line data. The delay compensation value is decided from reference delay compensation values of reference pixels among the pixels.

Abstract: A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

Abstract: An I2C router system includes an I2C router part, a first slave device and a second slave device. The I2C router part includes a first I2C router configured to output a first I2C signal via a first I2C bus, and a second I2C router configured to output a second I2C signal via a second I2C bus. The first slave device can be configured to receive the first I2C signal via the first I2C bus. The second slave device can be configured to receive the second I2C signal via the second I2C bus.

Abstract: A display apparatus includes a plurality of pixels connected to a plurality of gate lines and a plurality of data lines and a timing controller, in which each pixel includes a first sub-pixel and a second sub-pixel. In such a display apparatus, the timing controller provides the first sub-pixel and the second sub-pixel with a first data signal and a second data signal corresponding to one of a high gray scale curve and a low gray scale curve, alternately every frame, when the image signal is a first type of image signal, and the timing controller provides the first sub-pixel with a first data signal corresponding to the high gray scale curve and the second sub-pixel with a second data signal corresponding to the low gray scale curve when the image signal is a first type of image signal.

Abstract: A liquid crystal display includes a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a plurality of pixels. The timing controller receives an image data, compares a previous line data with a present line data to determine whether the present line data needs to be compensated, and generates a first modulation line data. In addition, the timing controller calculates the first modulation data and a delay compensation value to generate a second modulation line data. The delay compensation value is decided from reference delay compensation values of reference pixels among the pixels.

Abstract: An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the input data is generated on the basis of bit signals (a0-a15, b0-b15) for the portion from the 1st digit to the 15th digit of the input data, and of carry signal CIN input to the 1st digit, and it is output from CLA 204. Then, carry signal c15 from the 16th digit to the 17th digit is generated based on said generated carry signal c14 and bit signals (a15, b15) of the 16th digit of the input data, and this is output from CIA 205. Exclusive-NOR circuit 206 then operates on said carry signals c14 and c15, and overflow detection signal OVF16 is generated.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110a) connected to at least one of the Booth encoder cells (104a) and a plurality of Wallace tree cells (112a) connected to at least one of the Booth decoder cells (110a). Moreover, at least one first Wallace tree cell (112a1) or at least one first Booth decoder cell (110a1), or any combination thereof, includes a first plurality of transistors, and at least one second Wallace tree cell (112a2) or at least one second Booth decoder cell (110a2), or any combination thereof, includes a second plurality of transistors. In addition, at least one critical path of the multiply-accumulate module (100) includes the at least one first cell and a width of at least one of the first plurality of transistors is greater than a width of at least one of the second plurality of transistors.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.