Patents by Inventor Akihisa Iwamoto
Akihisa Iwamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250027269Abstract: Provided are a napped artificial leather which can restrain spontaneous elongation during the production process, enables the constant load elongation transverse/machine ratio to be set to an appropriate value even without a scrim or a liner, and is excellent in pilling resistance and appearance, and a method of producing the napped artificial leather. The napped artificial leather includes a nonwoven fabric which is an entangled body of microfine fibers, and a high-molecular elastic body attached to the nonwoven fabric, has a napped surface formed by napping the microfine fiber on at least one surface, and satisfies the following conditions (1) and (2):(1) the nonwoven fabric is composed of microfine polyester filaments and (2) the fiber density D1 in the transverse direction is from 150 to 450 fibers/mm2, the fiber density D2 in the machine direction is from 150 to 450 fibers/mm2, and D1/D2 is from 0.7 to 1.1.Type: ApplicationFiled: December 6, 2022Publication date: January 23, 2025Applicant: Kuraray Co., Ltd.Inventors: Akihisa Iwamoto, Masashi Meguro, Hiroyuki Hishida
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Patent number: 11697750Abstract: Disclosed is a polyurethane hot-melt adhesive including: a thermoplastic polyurethane that is a reactant of a raw material including a polymer polyol, a polyisocyanate, and a chain extender, wherein X?Y?15, where X represents a temperature (° C.) at which the polyurethane hot-melt adhesive has a melt viscosity of 2.0×103 Pa·s, and Y represents a temperature at which the polyurethane hot-melt adhesive has a melt viscosity of 1.0×105 Pa·s, and the polyurethane hot-melt adhesive has a 100% modulus of 2.5 MPa or more.Type: GrantFiled: July 24, 2018Date of Patent: July 11, 2023Assignee: KURARAY CO., LTD.Inventors: Masato Warita, Akihisa Iwamoto, Michinori Fujisawa
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Patent number: 11499266Abstract: Disclosed is a grain-finished artificial leather including an artificial leather base material, and a grain layer stacked on the artificial leather base material. The artificial leather base material includes a fiber-entangled body including ultrafine fibers having an average fineness of 0.4 dtex or less, an elastic polymer, and fine particles having an average particle size of 10 ?m or less. The content ratio of the fine particles is 10 to 40 mass %, and the ratio of the elastic polymer to the total amount of the elastic polymer and the fine particles is 20 to 80 mass %. Also, a total of an apparent density of the elastic polymer and an apparent density of the fine particles is 0.23 to 0.55 g/cm3.Type: GrantFiled: May 21, 2018Date of Patent: November 15, 2022Assignee: KURARAY CO., LTD.Inventors: Kimio Nakayama, Hayaki Sato, Naoto Narumoto, Akihisa Iwamoto
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Publication number: 20220333299Abstract: A napped artificial leather includes: a non-woven fabric that is art entangled body of ultrafine fibers, and an elastic polymer applied into the non-woven fabric; where the napped artificial leather has, on at least one side thereof, a napped surface formed by napping the ultrafine fibers. Each of the ultrafine fibers is art ultrafine fiber having a fineness of 0.5 dtex or less, and a tensile strength of 6 to 9 mN. A plurality of the ultrafine fibers form a fiber bundle, and the ultrafine fibers that form the fiber bundle are not constrained by the elastic polymer in a region of the napped artificial leather other than a surface layer portion. A content ratio of the elastic polymer is 16 to 40 mass %, and the napped artificial leather has an apparent density of 0.38 g/cm3 or more.Type: ApplicationFiled: September 3, 2020Publication date: October 20, 2022Applicant: KURARAY CO., LTD.Inventors: Akihisa Iwamoto, Masashi Meguro, Hiroyuki Hishida, Kiyofumi Enomoto
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Publication number: 20220074133Abstract: Disclosed is a napped artificial leather including: a fiber-entangled body including ultrafine fibers having a fineness of 0.5 dtex or less; and an elastic polymer impregnated into the fiber-entangled body, the napped artificial leather having a thickness of 0.25 to 1.5 mm, and including a main surface that is a napped surface formed by napping the ultrafine fibers. The napped artificial leather further includes phosphorous-based flame retard ant particles attached to the elastic polymer such as a polyurethane, the phosphorous-based flame retardant particles being locally present in a range of a thickness of 200 pm or less from a back surface opposite to the main surface. The phosphorous-based flame retardant particles have an average particle size of 0.1 to 30 ?m, a phosphorus atom content of 14 mass % or more, and a solubility in water at 30° C. of 0.2 mass % or less, and a melting point, or, in the absence of a melting point, a decomposition temperature, of 150° C.Type: ApplicationFiled: November 28, 2019Publication date: March 10, 2022Applicant: KURARAY CO., LTD.Inventors: Kimio NAKAYAMA, Akihisa IWAMOTO, Masashi MEGURO
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Publication number: 20210130664Abstract: Disclosed is a polyurethane hot-melt adhesive including: a thermoplastic polyurethane that is a reactant of a raw material including a polymer polyol, a polyisocyanate, and a chain extender, wherein X?Y?15, where X represents a temperature (° C.) at which the polyurethane hot-melt adhesive has a melt viscosity of 2.0×103 Pa·s, and Y represents a temperature at which the polyurethane hot-melt adhesive has a melt viscosity of 1.0×105 Pa·s, and the polyurethane hot-melt adhesive has a 100% modulus of 2.5 MPa or more.Type: ApplicationFiled: July 24, 2018Publication date: May 6, 2021Applicant: KURARAY CO., LTD.Inventors: Masato WARITA, Akihisa IWAMOTO, Michinori FUJISAWA
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Patent number: 10989958Abstract: A display device includes a display panel in which display pixels including colored pixels of a plurality of colors are arranged, an illumination device including a light source and configured to illuminate the display panel with light, and a control substrate configured to control drive of the display pixels, wherein the control substrate includes a display data generation circuit configured to generate display data for driving the display pixels, based on image data supplied from an external image signal supply source, a detection circuit configured to detect a change in luminance light modulation data for modulating luminance of the light source, supplied from an external image signal supply source, and a display data correction circuit configured to correct the display data, based on an output value of the detection circuit.Type: GrantFiled: March 13, 2020Date of Patent: April 27, 2021Assignee: SHARP KABUSHIKI KAISHAInventor: Akihisa Iwamoto
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Publication number: 20200301180Abstract: A display device includes a display panel in which display pixels including colored pixels of a plurality of colors are arranged, an illumination device including a light source and configured to illuminate the display panel with light, and a control substrate configured to control drive of the display pixels, wherein the control substrate includes a display data generation circuit configured to generate display data for driving the display pixels, based on image data supplied from an external image signal supply source, a detection circuit configured to detect a change in luminance light modulation data for modulating luminance of the light source, supplied from an external image signal supply source, and a display data correction circuit configured to correct the display data, based on an output value of the detection circuit.Type: ApplicationFiled: March 13, 2020Publication date: September 24, 2020Inventor: AKIHISA IWAMOTO
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Publication number: 20200277730Abstract: Disclosed is a grain-finished artificial leather including an artificial leather base material, and a grain layer stacked on the artificial leather base material. The artificial leather base material includes a fiber-entangled body including ultrafine fibers having an average fineness of 0.4 dtex or less, an elastic polymer, and fine particles having an average particle size of 10 ?m or less. The content ratio of the fine particles is 10 to 40 mass %, and the ratio of the elastic polymer to the total amount of the elastic polymer and the fine particles is 20 to 80 mass %. Also, a total of an apparent density of the elastic polymer and an apparent density of the fine particles is 0.23 to 0.55 g/cm3.Type: ApplicationFiled: May 21, 2018Publication date: September 3, 2020Applicant: KURARAYCO., LTD.Inventors: Kimio NAKAYAMA, Hayaki SATO, Naoto NARUMOTO, Akihisa IWAMOTO
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Publication number: 20190108781Abstract: A display device includes: a plurality of source lines extending in a first direction; and a plurality of gate lines extending in a second direction that intersects with the first direction. A plurality of switching elements are connected to one of the plurality of source lines. Each of the plurality of switching elements is connected to one of the plurality of gate lines. The plurality of switching elements connected to the source line are aligned in the first direction so as to be alternately located on the right and left sides of the source line. A plurality of picture elements that include the plurality of switching elements connected to the source line correspond to the same color.Type: ApplicationFiled: September 29, 2018Publication date: April 11, 2019Inventor: AKIHISA IWAMOTO
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Patent number: 9666140Abstract: The invention provides a gate-in-panel display device capable of preventing deterioration of thin-film transistors during pause drive, as well as a method for driving the same. At the end of a drive period, an active clear signal is provided to thin-film transistors in unit circuits, each thin-film transistor being connected to either a first or second node at a gate terminal, thereby bringing the thin-film transistors into ON state. As a result, the voltages of the first and second nodes are set to a reference voltage. Thus, even if a pause period lasts for a long period of time, the gate terminals of the thin-film transistors are not subjected to sustained voltage application, leading to no threshold voltage shifts.Type: GrantFiled: December 6, 2013Date of Patent: May 30, 2017Assignee: Sharp Kabushiki KaishaInventors: Jun Nakata, Masami Ozaki, Akihisa Iwamoto, Tomohiko Nishimura, Kohji Saitoh, Masaki Uehata
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Patent number: 9570030Abstract: A gate driver (24) which is provided by an IGZO-GDM and a level shifter circuit (13) are connected to each other via a first through a fifth wires (OL1 through OL5). Each wire (OL) is connected to a discharge unit (190). If an electric power supply to a first through a fifth output circuits (OC1 through OC5) in the level shifter circuit (13) becomes lower than a lower operation limit value during a power-off sequence which is supposed to remove a residual charge from inside a panel, outputs from the first through the fifth output circuits (OC1 through OC5) assume a high-impedance state, whereupon a potential on each wire (OL) is drawn by a discharge unit (190) into a ground potential. Therefore, residual charge inside the panel is removed quickly and stably when power supply is shut off.Type: GrantFiled: October 11, 2013Date of Patent: February 14, 2017Assignee: Sharp Kabushiki KaishaInventors: Akihisa Iwamoto, Masami Ozaki, Tomohiko Nishimura, Kohji Saitoh, Masaki Uehata, Jun Nakata
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Patent number: 9530384Abstract: In a display device that can use a low frequency drive method, in the case of low frequency drive, in a data correction unit (23) of a display control circuit (200), a pixel grayscale value is set such that the differential value between the potential difference between the pixel electrode and the common electrode when a voltage of positive polarity is applied and the potential difference between the pixel electrode and the common electrode when a voltage of negative polarity is applied becomes larger than during normal drive. With this, a correction amount (shift amount) is made larger during low frequency drive than during normal drive, whereby flickers and ghosting during low frequency drive are prevented.Type: GrantFiled: November 8, 2013Date of Patent: December 27, 2016Assignee: Sharp Kabushiki KaishaInventors: Kohji Saitoh, Akihisa Iwamoto, Tomohiko Nishimura, Masaki Uehata, Jun Nakata, Masami Ozaki
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Patent number: 9495929Abstract: A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intType: GrantFiled: March 5, 2013Date of Patent: November 15, 2016Assignee: Sharp Kabushiki KaishaInventors: Satoshi Horiuchi, Shinya Tanaka, Akira Tagawa, Yasuaki Iwase, Takayuki Mizunaga, Akihisa Iwamoto
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Patent number: 9355606Abstract: A liquid crystal display device includes: a data signal line; a scan signal line; a pixel electrode; a transistor connected to (i) the data signal line, (ii) the scan signal line, and (iii) the pixel electrode; and a common electrode, the liquid crystal display device being configured to turn on the transistor during a power-off sequence by causing a change in an electric potential of the scan signal line, the electric potential of the scan signal line reaching a first electric potential at a first timing after the change is initiated, and the common electrode being in an electrically floating state at a second timing which comes after the first timing.Type: GrantFiled: January 25, 2013Date of Patent: May 31, 2016Assignee: Sharp Kabushiki KaishaInventors: Kohji Saitoh, Akihisa Iwamoto, Masami Ozaki, Masaki Uehata, Jun Nakata, Tomohiko Nishimura
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Patent number: 9311881Abstract: Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged.Type: GrantFiled: August 9, 2012Date of Patent: April 12, 2016Assignee: Sharp Kabushiki KaishaInventors: Akihisa Iwamoto, Hideki Morii, Takayuki Mizunaga, Kazuya Nakaminami, Satoshi Horiuchi
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Patent number: 9293094Abstract: The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (t14 to t15), a netB discharge step (t15 to t16), and a netA discharge step (t16 to t17).Type: GrantFiled: August 3, 2012Date of Patent: March 22, 2016Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Morii, Akihisa Iwamoto, Satoshi Horiuchi, Takayuki Mizunaga, Kazuya Nakaminami
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Publication number: 20150332632Abstract: The invention provides a gate-in-panel display device capable of preventing deterioration of thin-film transistors during pause drive, as well as a method for driving the same. At the end of a drive period, an active clear signal is provided to thin-film transistors in unit circuits, each thin-film transistor being connected to either a first or second node at a gate terminal, thereby bringing the thin-film transistors into ON state. As a result, the voltages of the first and second nodes are set to a reference voltage. Thus, even if a pause period lasts for a long period of time, the gate terminals of the thin-film transistors are not subjected to sustained voltage application, leading to no threshold voltage shifts.Type: ApplicationFiled: December 6, 2013Publication date: November 19, 2015Inventors: Jun NAKATA, Masami OZAKI, Akihisa IWAMOTO, Tomohiko NISHIMURA, Kohji SAITOH, Masaki UEHATA
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Publication number: 20150332650Abstract: Provided are a display device capable of preventing burning by suppressing occurrence of a VCOM shift which occurs when a liquid crystal panel is driven for a long period of time, and a drive method thereof. Since a source output voltage corresponding to each of tone levels from a tone value 0 to a tone value 224 agrees with a flicker regulation voltage, a shift amount from the flicker regulation voltage is set to 0 mV, and a source output voltage corresponding to a tone value 255 is obtained by further adding +40 mV as a shift amount to 4.05 V which is the flicker regulation voltage. In such a manner, a source output voltage, increased at a high tone level and in the vicinity thereof, is applied to source bus lines SL1 to SLm and written into each liquid crystal capacitance Ccl.Type: ApplicationFiled: December 6, 2013Publication date: November 19, 2015Inventors: Kohji SAITOH, Akihisa IWAMOTO, Jun NAKATA, Masaki UEHATA, Tomohiko NISHIMURA, Ichiro UMEKAWA, Masami OZAKI
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Publication number: 20150279333Abstract: In a display device that can use a low frequency drive method, in the case of low frequency drive, in a data correction unit (23) of a display control circuit (200), a pixel grayscale value is set such that the differential value between the potential difference between the pixel electrode and the common electrode when a voltage of positive polarity is applied and the potential difference between the pixel electrode and the common electrode when a voltage of negative polarity is applied becomes larger than during normal drive. With this, a correction amount (shift amount) is made larger during low frequency drive than during normal drive, whereby flickers and ghosting during low frequency drive are prevented.Type: ApplicationFiled: November 8, 2013Publication date: October 1, 2015Inventors: Kohji Saitoh, Akihisa Iwamoto, Tomohiko Nishimura, Masaki Uehata, Jun Nakata, Masami Ozaki