Patents by Inventor Akihito Yamamoto

Akihito Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190006419
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Application
    Filed: August 14, 2018
    Publication date: January 3, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
  • Publication number: 20180325946
    Abstract: The present invention provides a damaged part treatment composition for repairing a damaged part of a target tissue that includes a stem cell-conditioned medium obtained by culturing stem cells; a damaged part treatment method for repairing or restoring a damaged part of a target tissue that includes administering the damaged part treatment composition to a patient having the target tissue for the damaged part treatment composition in an amount therapeutically effective for repairing the damaged part of the target tissue; a method of treating cerebral infarction that includes administering the damaged part treatment composition to a cerebral infarct patient in an amount effective for repairing a damaged part of the brain; and a method of treating a CNS disease that includes administering, as a CNS disease treatment composition, the damaged part treatment composition to a CNS disease patient in a therapeutically effective amount.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: Minoru Ueda, Yoichi Yamada, Katsumi Ebisawa, Akihito Yamamoto, Kiyoshi Sakai, Kohki Matsubara, Hisashi Hattori, Masahiko Sugiyama, Takanori Inoue
  • Publication number: 20180311313
    Abstract: A composition having tissue repair activity, which is capable of promoting reactions associated with tissue repair, contains at least one selected from the group consisting of a first component that is a protein having a monocyte chemotactic protein-1 (MCP-1) activity, a second component that is a protein having the extracellular domain activity of sialic acid-binding immunoglobulin-type lectin-9 (Siglec-9), and a third component that is at least one of chondroitin sulfate and chondroitin sulfate proteoglycan.
    Type: Application
    Filed: March 28, 2018
    Publication date: November 1, 2018
    Inventors: Akihito YAMAMOTO, Minoru UEDA, Kohki MATSUBARA, Akio SUZUMURA, Koichi FURUKAWA, Yoshihiro MATSUSHITA, Hirotaka WAKAYAMA, Nobunori TAKAHASHI, Shin TSUNEKAWA, Takako IZUMOTO
  • Publication number: 20180252364
    Abstract: Provided is a fluid supply device capable of reducing loads to be applied to pipings while increasing tolerable rotation amounts of respective nozzles around a predetermined rotation axis. A fluid supply device 5 includes first pipings 31A to 31L connected to nozzles 11A to 11C and 12F to 12J, a rotary support part 10 supporting the nozzles 11A to 11C and 12F to 12J and the first pipings 31A to 31L, second flexible pipings 33A to 33L, and a linear guide 15. One end portions 33a of the second flexible pipings 33A to 33L are configured to rotate around a rotation axis L1 in conjunction with the respective first pipings 31A to 31L. A movable guide portion 51 of the linear guide 15 is configured to be linearly displaceable along with deforming movements of the respective second flexible pipings 33A to 33L caused by rotations of the respective first pipings 31A to 31L.
    Type: Application
    Filed: May 2, 2016
    Publication date: September 6, 2018
    Applicant: Koyo Thermo Systems Co., Ltd.
    Inventors: Akihito YAMAMOTO, Yasuhiro SASAKI
  • Patent number: 10056433
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 21, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
  • Patent number: 9962428
    Abstract: A composition having tissue repair activity, which is capable of promoting reactions associated with tissue repair, contains at least one selected from the group consisting of a first component that is a protein having a monocyte chemotactic protein-1 (MCP-1) activity, a second component that is a protein having the extracellular domain activity of sialic acid-binding immunoglobulin-type lectin-9 (Siglec-9), and a third component that is at least one of chondroitin sulfate and chondroitin sulfate proteoglycan.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: May 8, 2018
    Assignee: NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Akihito Yamamoto, Minoru Ueda, Kohki Matsubara, Akio Suzumura, Koichi Furukawa, Yoshihiro Matsushita, Hirotaka Wakayama, Nobunori Takahashi, Shin Tsunekawa, Takako Izumoto
  • Publication number: 20180111439
    Abstract: A damping force control apparatus for a suspension is applied to a damper whose damping force can be set based on a damping force control value and controls the damping force control value. The damper is attached to a support portion with a buffer member interposed between the support portion of a vehicle body and a cylinder of the damper. The apparatus includes: a displacement related quantity estimation device estimating relative displacement of a vehicle wheel and a relative speed of the vehicle wheel with respect to the vehicle body as estimated relative displacement and an estimated relative speed; and a damping force control value calculation device determining the damping force control value so as to suppress vibration of the vehicle body based on state variables provided from the vehicle body and the estimated relative speed.
    Type: Application
    Filed: October 23, 2017
    Publication date: April 26, 2018
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Akihito YAMAMOTO, Wataru TANAKA
  • Publication number: 20180050509
    Abstract: Provided is a tank cooling device that is capable of cooling a tank more quickly. A tank cooling device 4 has a nozzle 40. The nozzle 40 is comprised to supply cooling gas for cooling a tank 100 to an outer surface of the tank 100, with the cooling gas assisted by compressed gas in the nozzle 40. The tank 100 has a tank main body 101 made by using synthetic resin and an end member 102 made by using metal. The nozzle 40 supplies a gas flow to each of the tank main body 101 and the end member 102.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 22, 2018
    Applicant: Koyo Thermo Systems Co., Ltd.
    Inventors: Akihito YAMAMOTO, Yasuhiro SASAKI, Iwao MORIMOTO
  • Patent number: 9889717
    Abstract: A damping force control apparatus controlling a damping force control value for a damper whose damping force is set by the damping force control value includes: a relative velocity estimation device estimating a relative velocity of a vehicle wheel with respect to a vehicle body; and a damping force calculation device determining the damping force control value to control vibration of the vehicle body based on control input variables of the vehicle body and an estimated relative velocity, wherein the relative velocity estimation device includes an estimated damping force calculation section, a delay correction section, and a relative velocity calculation section, and the delay correction section corrects the estimated damping force and varies delay correction terms to reduce divergence between an actual measured relative velocity and the estimated relative velocity in different damping coefficients of the damper.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 13, 2018
    Assignee: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Akihito Yamamoto, Wataru Tanaka, Takafumi Makino
  • Publication number: 20160351621
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Application
    Filed: August 8, 2016
    Publication date: December 1, 2016
    Inventors: Masahiro KIYOTOSHI, Akihito YAMAMOTO, Yoshio OZAWA, Fumitaka ARAI, Riichiro SHIROTA
  • Patent number: 9450181
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
  • Publication number: 20160176259
    Abstract: A damping force control apparatus controlling a damping force control value for a damper whose damping force is set by the damping force control value includes: a relative velocity estimation device estimating a relative velocity of a vehicle wheel with respect to a vehicle body; and a damping force calculation device determining the damping force control value to control vibration of the vehicle body based on control input variables of the vehicle body and an estimated relative velocity, wherein the relative velocity estimation device includes an estimated damping force calculation section, a delay correction section, and a relative velocity calculation section, and the delay correction section corrects the estimated damping force and varies delay correction terms to reduce divergence between an actual measured relative velocity and the estimated relative velocity in different damping coefficients of the damper.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 23, 2016
    Applicant: Aisin Seiki Kabushiki Kaisha
    Inventors: Akihito YAMAMOTO, Wataru TANAKA, Takafumi MAKINO
  • Publication number: 20150366917
    Abstract: A composition for preventing or treating inflammatory disease and that is effective for inflammatory disease such as fulminant hepatitis and interstitial pneumonia. For such an objective, the present uses a culture supernatant obtained by culturing dental pulp stem cells as the active ingredient of the composition for preventing or treating inflammatory disease.
    Type: Application
    Filed: February 13, 2014
    Publication date: December 24, 2015
    Inventors: Akihito YAMAMOTO, Minoru UEDA, Hidemi GOTO, Masatoshi ISHIGAMI, Yoshihiro MATSUSHITA, Yoshinori HASEGAWA, Naozumi HASHIMOTO, Hirotaka WAKAYAMA
  • Publication number: 20150352187
    Abstract: A composition having tissue repair activity, which is capable of promoting reactions associated with tissue repair, contains at least one selected from the group consisting of a first component that is a protein having a monocyte chemotactic protein-1 (MCP-1) activity, a second component that is a protein having the extracellular domain activity of sialic acid-binding immunoglobulin-type lectin-9 (Siglec-9), and a third component that is at least one of chondroitin sulfate and chondroitin sulfate proteoglycan.
    Type: Application
    Filed: December 24, 2013
    Publication date: December 10, 2015
    Inventors: Akihito YAMAMOTO, Minoru UEDA, Kohki MATSUBARA, Akio SUZUMURA, Koichi FURUKAWA, Yoshihiro MATSUSHITA, Hirotaka WAKAYAMA, Nobunori TAKAHASHI, Shin TSUNEKAWA, Takako IZUMOTO
  • Publication number: 20140264227
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiro KIYOTOSHI, Akihito YAMAMOTO, Yoshio OZAWA, Fumitaka ARAI, Riichiro SHIROTA
  • Patent number: 8766373
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
  • Patent number: 8637915
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Patent number: 8609487
    Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto, Katsuyuki Sekine, Ryota Fujitsuka, Daisuke Nishida, Yoshio Ozawa
  • Publication number: 20130328959
    Abstract: An image forming apparatus includes a conveying section for withdrawing and conveying a printing medium stored in the form of a roll, a printing section for effecting a printing operation on the printing medium, a decurling device for correcting curling in the printing medium and a controlling section. The decurling device is disposed on the downstream side of the printing section. The controlling section controls such that a decurling operation to be effected before the printing operation and a decurling operation to be effected after the printing operation are effected by the decurling device.
    Type: Application
    Filed: May 20, 2013
    Publication date: December 12, 2013
    Applicant: NK WORKS CO., LTD.
    Inventors: Toshiro AKIRA, Akihito YAMAMOTO, Hisashi OMORI
  • Patent number: D737163
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 25, 2015
    Inventors: Akihito Yamamoto, Kazumasa Kato, Toshihiro Mori