Abstract: A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer.

Abstract: A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer.

Abstract: A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer.

Abstract: In transistor layout design, a plurality of distances Lfig1, Lfig2, Lfig3 from a gate electrode of a transistor to the edge of a diffusion layer are displayed by multiple lines according to a variation amount of a transistor characteristic with the use of a CAD tool. A layer for defining an isolation region between adjacent transistors is extended automatically by the CAD tool. Accordingly, even in the case where the transistor characteristic varies depending on the distance from the gate electrode of the transistor to the edge of the diffusion layer, the isolation region between the adjacent transistors can be layouted and designed optimally with no measurement of the distance by designer's visual observation necessitated.

Abstract: In transistor layout design, a plurality of distances Lfig1, Lfig2, Lfig3 from a gate electrode of a transistor to the edge of a diffusion layer are displayed by multiple lines according to a variation amount of a transistor characteristic with the use of a CAD tool. A layer for defining an isolation region between adjacent transistors is extended automatically by the CAD tool. Accordingly, even in the case where the transistor characteristic varies depending on the distance from the gate electrode of the transistor to the edge of the diffusion layer, the isolation region between the adjacent transistors can be layouted and designed optimally with no measurement of the distance by designer's visual observation necessitated.

Abstract: A semiconductor integrated circuit with integrated memory and data-processing logic portions is provided, with which productivity and yield can be improved. The semiconductor integrated circuit is provided with a memory, a plurality of logic portions that are capable of being connected to the memory, and a separation portion that connects one of the plurality of logic portions to the memory, while separating the other logic portions from the memory. One required logic portion of the plurality of logic portions is connected to the memory, and the other non-required logic portions are separated from the memory, by the separation portion. The semiconductor integrated circuit can be switched for a system LSI after wafer processing, so this enables a plurality of system LSIs to be manufactured using the same exposure masks, thus improving productivity. Furthermore, defective logic portions can be recovered, thus improving the yield.

Abstract: A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer.

Abstract: A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.

Abstract: A semiconductor memory device according to the present invention includes: a plurality of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells arranged in an array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and a plurality of dummy transistors 32-j each of which is formed between two adjacent ones of the plurality of N-ch MOS transistors 30-k so as to share diffusion layers with adjacent N-ch MOS transistors 30 and each of which has a gate electrode supplied with a voltage for electrically insulating these adjacent transistors 30-k.

Abstract: A semiconductor memory device according to the present invention includes: a plurality of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells arranged in an array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and a plurality of dummy transistors 32-j each of which is formed between two adjacent ones of the plurality of N-ch MOS transistors 30-k so as to share diffusion layers with adjacent N-ch MOS transistors 30 and each of which has a gate electrode supplied with a voltage for electrically insulating these adjacent transistors 30-k.

Abstract: A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.

Abstract: A semiconductor integrated circuit with integrated memory and data-processing logic portions is provided, with which productivity and yield can be improved. The semiconductor integrated circuit is provided with a memory, a plurality of logic portions that are capable of being connected to the memory, and a separation portion that connects one of the plurality of logic portions to the memory, while separating the other logic portions from the memory. One required logic portion of the plurality of logic portions is connected to the memory, and the other non-required logic portions are separated from the memory, by the separation portion. The semiconductor integrated circuit can be switched for a system LSI after wafer processing, so this enables a plurality of system LSIs to be manufactured using the same exposure masks, thus improving productivity. Furthermore, defective logic portions can be recovered, thus improving the yield.

Abstract: In a semiconductor memory device with a plurality of banks having a plurality of memory sub array, according to a mode setting signal, data access control is made depending on whether access is made on a memory sub array basis or a bank basis. A multi-bank semiconductor memory device is provided capable of easily implementing both of a low power consumption mode and a long page size mode.

Abstract: A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time.

Abstract: In a semiconductor memory device with a plurality of banks having a plurality of memory sub array, according to a mode setting signal, data access control is made depending on whether access is made on a memory sub array basis or a bank basis. A multi-bank semiconductor memory device is provided capable of easily implementing both of a low power consumption mode and a long page size mode.

Abstract: A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time.

Abstract: A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time.

Abstract: In a semiconductor storage device, a dummy redundancy decision circuit detects the endpoint of redundancy decision made by a column redundancy decision circuit and outputs a end-of-redundancy-decision signal RED. Responsive to the signal RED, a control signal generator outputs normal and redundant column control signals NEN and REN to normal and redundant column decoders, respectively, based on a result of the redundancy decision made by the column redundancy decision circuit and represented by a signal XSYP. Accordingly, a time a normal column select signal Y is output to select a normal column and a time a redundant column select signal SY is output to select a redundant column are both later than a reference time by an interval of the same length. In addition, the interval between the end of data line pre-charging and the start of data line potential amplification can be shortened. As a result, data can be read out much faster.

Abstract: Each sub-word line drive circuit SWD in a sub-word line drive section SWLB receives a signal carried by a main word line MWL0, a sub-word line non-selection signal XWD, and a sub-word line drive signal WD to drive a sub-word line SW. The sub-word line non-selection signal XWD is generated by an inverter XWDG in an intersection region SDR based on the sub-word line drive signal WD received by the inverter. The active level of the sub-word line drive signal WD is an internal boosted potential VPP which is higher than the external supply potential VDD. By using as the inactive level of the sub-word line non-selection signal XWD an internal lowered potential VINT which is lower than the external supply potential VDD, power consumption of an internal boosted potential generation circuit is reduced.

Abstract: A semiconductor integrated circuit including an internal voltage step down circuit exhibits a first voltage characteristic I having substantially no dependence on an external power supply voltage VEXT and holding an internal power supply voltage VINT at a constant voltage VA if the external power supply voltage VEXT is in the range between two predetermined values V1 and V2. On and after the external power supply voltage VEXT exceeds the predetermined value V2, the circuit exhibits a second voltage characteristic II, in which the internal power supply voltage VINT varies from the constant voltage VA in accordance with the external power supply voltage VEXT, during a non-accelerated test (operation margin certification test). On the other hand, during the accelerated test, the circuit exhibits a third voltage characteristic III in which the internal power supply voltage VINT reaches a certain voltage VB (>VA) and goes on increasing from VB in accordance with the external power supply voltage VEXT.