Patents by Inventor Akio Kaneko
Akio Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20100003813Abstract: According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.Type: ApplicationFiled: September 11, 2009Publication date: January 7, 2010Inventors: Katsuyuki Sekine, Akio Kaneko, Motoyuki Sato, Seiji Inumiya, Kazuhiro Eguchi
-
Patent number: 7629243Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.Type: GrantFiled: July 18, 2006Date of Patent: December 8, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
-
Publication number: 20090194821Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.Type: ApplicationFiled: January 26, 2009Publication date: August 6, 2009Inventors: Akio KANEKO, Seiji Inumiya, Tomonori Aoyama, Takuya Kobayashi
-
Patent number: 7521309Abstract: A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layerType: GrantFiled: November 30, 2007Date of Patent: April 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Motoyuki Sato, Katsuyuki Sekine, Tomohiro Saito, Kazuaki Nakajima, Tomonori Aoyama
-
Patent number: 7501335Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a silicate film containing metal on a substrate; and introducing nitrogen and deuterium into the silicate film by using ND3 gas.Type: GrantFiled: December 1, 2004Date of Patent: March 10, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Yoshitaka Tsunashima, Seiji Inumiya, Akio Kaneko, Motoyuki Sato, Kazuhiro Eguchi
-
Publication number: 20090000547Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.Type: ApplicationFiled: August 14, 2008Publication date: January 1, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Akio Kaneko, Kazuhiro Eguchi
-
Publication number: 20080265324Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.Type: ApplicationFiled: April 22, 2008Publication date: October 30, 2008Inventors: Akio Kaneko, Seiji Inumiya, Katsuyuki Sekine, Kazuhiro Eguchi, Motoyuki Sato
-
Patent number: 7427518Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.Type: GrantFiled: October 28, 2005Date of Patent: September 23, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Akio Kaneko, Kazuhiro Eguchi
-
Publication number: 20080220582Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask matType: ApplicationFiled: April 2, 2008Publication date: September 11, 2008Inventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
-
Publication number: 20080191271Abstract: A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate.Type: ApplicationFiled: January 10, 2008Publication date: August 14, 2008Inventors: Atsushi YAGISHITA, Akio KANEKO
-
Publication number: 20080146013Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.Type: ApplicationFiled: January 31, 2008Publication date: June 19, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
-
Publication number: 20080138969Abstract: A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layerType: ApplicationFiled: November 30, 2007Publication date: June 12, 2008Inventors: Akio Kaneko, Motoyuki Sato, Katsuyuki Sekine, Tomohiro Saito, Kazuaki Nakajima, Tomonori Aoyama
-
Patent number: 7375403Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.Type: GrantFiled: December 18, 2003Date of Patent: May 20, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Seiji Inumiya, Katsuyuki Sekine, Kazuhiro Eguchi, Motoyuki Sato
-
Patent number: 7371644Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask matType: GrantFiled: April 17, 2006Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru
-
Publication number: 20080054378Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.Type: ApplicationFiled: August 10, 2007Publication date: March 6, 2008Inventors: Akio Kaneko, Kazuhiro Eguchi, Seiji Inumiya, Katsuyuki Sekine, Motoyuki Sato
-
Patent number: 7265427Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.Type: GrantFiled: August 27, 2004Date of Patent: September 4, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Kazuhiro Eguchi, Seiji Inumiya, Katsuyuki Sekine, Motoyuki Sato
-
Publication number: 20070197048Abstract: According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.Type: ApplicationFiled: April 19, 2007Publication date: August 23, 2007Inventors: Katsuyuki Sekine, Akio Kaneko, Motoyuki Sato, Seiji Inumiya, Kazuhiro Eguchi
-
Publication number: 20070190708Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.Type: ApplicationFiled: January 31, 2007Publication date: August 16, 2007Inventors: Akio Kaneko, Atsushi Yagishita, Satoshi Inaba
-
Publication number: 20070148843Abstract: This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.Type: ApplicationFiled: December 7, 2006Publication date: June 28, 2007Inventors: Tomohiro Saito, Akio Kaneko, Atsushi Yagishita
-
Patent number: 7220681Abstract: A semiconductor device including a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode; wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.Type: GrantFiled: February 4, 2005Date of Patent: May 22, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Akio Kaneko, Motoyuki Sato, Seiji Inumiya, Kazuhiro Eguchi