Patents by Inventor Akio SUGAHARA

Akio SUGAHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12159677
    Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 3, 2024
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • Publication number: 20240347087
    Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Zhao LU, Yuji NAGAI, Akio SUGAHARA, Takehisa KUROSAWA, Masaru KOYANAGI
  • Publication number: 20240321348
    Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 26, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Naomi TAKEDA, Masanobu SHIRAKAWA, Akio SUGAHARA
  • Patent number: 12087396
    Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: September 10, 2024
    Assignee: Kioxia Corporation
    Inventors: Takehisa Kurosawa, Akio Sugahara, Mitsuhiro Abe, Hisashi Fujikawa, Yuji Nagai, Zhao Lu
  • Publication number: 20240272833
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Applicant: Kioxia Corporation
    Inventors: Akio SUGAHARA, Yuji NAGAI
  • Patent number: 12062412
    Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: August 13, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Zhao Lu, Yuji Nagai, Akio Sugahara, Takehisa Kurosawa, Masaru Koyanagi
  • Patent number: 12033693
    Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: July 9, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Naomi Takeda, Masanobu Shirakawa, Akio Sugahara
  • Publication number: 20240221799
    Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Akio SUGAHARA, Yoshikazu HARADA, Shoichiro HASHIMOTO
  • Patent number: 12001723
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: June 4, 2024
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Yuji Nagai
  • Patent number: 11961583
    Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: April 16, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Akio Sugahara, Yoshikazu Harada, Shoichiro Hashimoto
  • Publication number: 20240111671
    Abstract: A memory system according to an embodiment includes: a first chip including a first plane and a first input/output circuit; and a controller which is capable of issuing a command for controlling the first chip. The first plane includes: a first memory cell array having a plurality of first memory cell transistors; and a first latch circuit which is capable of storing first read data read from the first memory cell array. The first input/output circuit includes a first FIFO circuit which is capable of fetching the first read data from the first latch circuit. The controller is capable of transmitting to the first chip a first command for ordering fetching of the first read data from the first latch circuit to the first FIFO circuit during a period in which a read operation is executed on the first plane.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 4, 2024
    Applicant: Kioxia Corporation
    Inventors: Akio SUGAHARA, Masaki FUJIU
  • Patent number: 11942180
    Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: March 26, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Zhao Lyu, Akio Sugahara, Takehisa Kurosawa, Yuji Nagai, Hisashi Fujikawa
  • Publication number: 20240094959
    Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Akio SUGAHARA, Zhao LU, Takehisa KUROSAWA, Yuji NAGAI
  • Patent number: 11915778
    Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Daisuke Arizono, Akio Sugahara, Mitsuhiro Abe, Mitsuaki Honma
  • Patent number: 11861226
    Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Zhao Lu, Takehisa Kurosawa, Yuji Nagai
  • Publication number: 20230420054
    Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Akio SUGAHARA, Akihiro IMAMOTO, Toshifumi WATANABE, Mami KAKOI, Kohei MASUDA, Masahiro YOSHIHARA, Naofumi ABIKO
  • Publication number: 20230395144
    Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 7, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Naomi TAKEDA, Masanobu SHIRAKAWA, Akio SUGAHARA
  • Patent number: 11783899
    Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: October 10, 2023
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Akihiro Imamoto, Toshifumi Watanabe, Mami Kakoi, Kohei Masuda, Masahiro Yoshihara, Naofumi Abiko
  • Publication number: 20230315343
    Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Akio SUGAHARA, Masahiro YOSHIHARA
  • Publication number: 20230317177
    Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: Kioxia Corporation
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA