Patents by Inventor Akira Aso
Akira Aso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7134891Abstract: A connector 1 according to the invention comprises a main body 10 for receiving the front end of a flat cable 2 being inserted therein, a movable pressurizing member 11 adapted to press and rigidly secure in position the flat cable 2 inserted into the main body 10 and projections 13 arranged either on the main body 10 or on the pressurizing member 11 so as to be engaged respectively with the corresponding holes 23 of the flat cable 2 when the front end of the flat cable is inserted into the connector 1 to take a right position in the connector 1. The flat cable 2 comprises a flexible base member 21 and wires 22 formed in the flexible base member 21, the flexible base member 21 being provided with holes 23 to be engaged respectively with the corresponding projections 13 arranged in the connector 1 when the flexible base member 21 is inserted into the connector 1 to take a right position in the connector 1.Type: GrantFiled: September 13, 2004Date of Patent: November 14, 2006Assignees: Sony Corporation, Molex Japan Co., Ltd.Inventors: Shun Kayama, Yukiko Shimizu, Masayoshi Iida, Tomisaburo Yamaguchi, Shinsuke Kunishi, Akira Aso
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Publication number: 20050208824Abstract: A connector 1 according to the invention comprises a main body 10 for receiving the front end of a flat cable 2 being inserted therein, a movable pressurizing member 11 adapted to press and rigidly secure in position the flat cable 2 inserted into the main body 10 and projections 13 arranged either on the main body 10 or on the pressurizing member 11 so as to be engaged respectively with the corresponding holes 23 of the flat cable 2 when the front end of the flat cable is inserted into the connector 1 to take a right position in the connector 1. The flat cable 2 comprises a flexible base member 21 and wires 22 formed in the flexible base member 21, the flexible base member 21 being provided with holes 23 to be engaged respectively with the corresponding projections 13 arranged in the connector 1 when the flexible base member 21 is inserted into the connector 1 to take a right position in the connector 1.Type: ApplicationFiled: September 13, 2004Publication date: September 22, 2005Applicants: Sony Corporation, Molex Japan Co., Ltd.Inventors: Shun Kayama, Yukiko Shimizu, Masayoshi Iida, Tomisaburo Yamaguchi, Shinsuke Kunishi, Akira Aso
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Publication number: 20040248472Abstract: The present invention is directed to an electrical connector having at least two terminals that are short-circuited to each other by the use of a continuous portion. The continuous portion is formed during the manufacturing process of the terminals, thereby simplifying short-circuiting of two or more terminals together.Type: ApplicationFiled: May 26, 2004Publication date: December 9, 2004Inventors: Akira Aso, Masami Sasao, Kazuya Takahashi
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Patent number: 5354214Abstract: An electrical connector is disclosed for interconnecting a flat flexible circuit to a printed circuit board. The connector includes a dielectric housing having an elongated mouth for receiving the flat flexible circuit. Terminals are mounted in the housing and are adapted for coupling appropriate conductors of the flat flexible circuit with circuit traces on the printed circuit board. An actuator has an elongated tongue for insertion into the mouth of the housing to maintain the flat flexible circuit in engagement with the terminals. At least one latch/mounting clip is mounted on the housing, and a complementary interengaging latch is provided between a first portion of the clip and the actuator to hold the actuator in its inserted position on the housing. A second portion of the clip is adapted for operative association with the printed circuit board.Type: GrantFiled: July 23, 1993Date of Patent: October 11, 1994Assignee: Molex IncorporatedInventors: Akira Aso, Russell J. Leonard, George M. Simmel
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Patent number: 5117134Abstract: The semiconductor level conversion device for an ECL circuit having a pair of transistors connected commonly at their emitters. A first gate circuit is connected to apply a first output signal to a base of one of the transistors, and a second gate circuit is connected to apply a second output signal to a base of the other of the transistors. The first and second output signals are held in-phase relation to each other. The first output signal has a high logic level lower than that of the second output signal and a low logic level higher than that of the second output signal.Type: GrantFiled: August 24, 1990Date of Patent: May 26, 1992Assignee: NEC CorporationInventor: Akira Aso
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Patent number: 4947233Abstract: A semi-custom LSI formed on a semiconductor chip includes a plurality of basic cells formed in a central portion of the semiconductor chip, a plurality of input/output cells formed in a peripheral portion of the semiconductor chip, a plurality of bonding pad formed on the input/output cells, and a wiring layer wiring circuit elements in the basic cells and the input/output cells to form a functional circuit and buffers and connecting between the functional circuit, the buffers and the bonding pads, at least one input/output cell having two bonding pads thereon, and one of the two bonding pads being located near an edge of the semiconductor chip, compared to the other.Type: GrantFiled: October 26, 1987Date of Patent: August 7, 1990Assignee: NEC CorporationInventor: Akira Aso
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Patent number: 4933575Abstract: There is provided a logic circuit formed of a flip-flop receiving an input data, a control signal, a set signal and a reset signal and producing an output signal and an inverted output signal. To this is added a first logic circuit performing a first logical arithmetic of the input data and the set signal to produce a first logic signal, and a second logic circuit performing a second logical arithmetic of the control signal and the reset signal to produce a second logic signal. A first selector circuit selects one of the first logic signal and the output signal and a second selector circuit selects one of the second logic signal and the inverted output signal thereby providing convesability between sequential and combination modes of operation.Type: GrantFiled: February 14, 1989Date of Patent: June 12, 1990Assignee: NEC CorporationInventor: Akira Aso
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Patent number: 4841352Abstract: A semiconductor integrated circuit such as a semi-custom LSI includes a semiconductor substrate, a plurality of circuit elements formed on the semiconductor substrate and aligned in a plural number of lines, selected one's of the circuit elements being used in an electrical circuit formed in the semiconductor integrated circuit, unselected one's of the circuit elements being left without used in the electrical circuit, at least one set of capacitor cells formed on but isolated from the unselected one of the circuit element, wirings formed in spaces between the lines of the circuit elements to interconnect the selected ones of the circuit elements, and a means for connecting at least one of the capacitor cells selected in the one set to one of wirings.Type: GrantFiled: June 14, 1988Date of Patent: June 20, 1989Assignee: NEC CorporationInventor: Akira Aso
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Patent number: 4526436Abstract: A connector assembly for electrically connecting the conductors of a flat flexible multi-conductor cable to another circuit member. The connector assembly includes a housing having the plurality of side by side, elongated open-ended terminal receiving cavities and a plurality of stamped U-shaped terminals received in the cavities. Each terminal has first and second arms extending up from the base of the body with a contact portion formed near the free end of one of the arms for making electrical contact with the cable conductor when the cable is received in the housing slot in the area between the two arms. The first arm includes a hooked-shaped engaging portion having the contact surface formed thereon that is disposed substantially vertical to and in projecting relation from the plane of the first arm at an acute angle relative to the longitudinal axis thereof.Type: GrantFiled: December 5, 1983Date of Patent: July 2, 1985Assignee: Molex IncorporatedInventor: Akira Aso
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Patent number: 4410222Abstract: An electrical connector assembly for electrically connecting insulation-clad ribbon cable to a circuit member. The connector assembly includes a female connector, which is connected to the ribbon cable, and a male connector or header, which is connected to said circuit member, and is adapted to mate with the female connector. Selectively removeable strain relief means are provided as part of the female connector. The male connector has a pair of improved, pivotly mounted manually manipulatable lever means for selectively ejecting or locking the female connector with the male connector. The lever means can positively lock and mate the female connector to the male connector whether or not the strain relief means is mounted on the female connector.Type: GrantFiled: July 6, 1981Date of Patent: October 18, 1983Assignee: Molex IncorporatedInventors: Masahiro Enomoto, Yoshiyuki Awano, Yuji Yamada, Akira Aso
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Patent number: 4326210Abstract: A field effect semiconductor device comprises a P-N junction with a depletion layer responsive to radiant energy for controllably enabling the field effect semiconductor device. The depletion layer occurs near at least a pair of gate locations within a silicon substrate. The gate locations are of P-type while the silicon substrate is of N-type. The depletion layer is rendered ineffective by photoelectromotive force derived from the radiant energy. A channel emerges according to the shrinkage of the depletion layer to thereby provide electrical connection between a source and drain electrodes of the field effect transistor.Type: GrantFiled: May 12, 1980Date of Patent: April 20, 1982Assignee: Sharp Kabushiki KaishaInventors: Akira Aso, Hitoshi Kawanabe
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Patent number: 4318115Abstract: A photoelectric semiconductor device is disclosed which exhibits a reduced spectral sensitivity in a desired wavelength zone. An N(P) type impurity region is formed in a P(N) type semiconductor substrate to establish a first PN junction functioning as a first photodiode. A P(N) type impurity region is shallowly formed in the N(P) type impurity region to establish a second PN junction functioning as a second photodiode. When the first PN junction is shunted, the photoelectric semiconductor device shows a spectral sensitivity which is reduced in the longer wavelength zone. Contrarily, when the second PN junction is shunted, the photoelectric semiconductor device shows the spectral sensitivity which is reduced in the shorter wavelength zone.Type: GrantFiled: July 24, 1979Date of Patent: March 2, 1982Assignee: Sharp Kabushiki KaishaInventors: Toshihumi Yoshikawa, Zempei Tani, Akira Aso, Hitoshi Kawanabe
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Patent number: 4309604Abstract: Disclosed is a solid state wavelength detection system responding to output signals derived from a photoelectric semiconductor device. The photoelectric semiconductor device comprise at least two PN junctions formed at different depth from the surface of the semiconductor substrate. A deeper PN junction develops an output signal related to longer wavelength component of the light impinging thereon. A shallower PN junction develops an output signal related to shorter wavelength component of the impinging light. These two output signals are logarithmically compressed and compared with each other. Difference of the logarithmically compressed output signals represents the wavelength information of the impinging light.Type: GrantFiled: July 24, 1979Date of Patent: January 5, 1982Assignee: Sharp Kabushiki KaishaInventors: Toshihumi Yoshikawa, Zempei Tani, Akira Aso, Hitoshi Kawanabe