Patents by Inventor Akira Fujimoto

Akira Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10859502
    Abstract: A method, to perform glow discharge optical emission spectrometry using a glow discharge tube equipped with an electrode having an end section, for producing a sample containing object that is to be disposed so as to be opposed to the end section, comprises: covering one end of a sample holding section having a cylindrical shape and being open at both ends using a covering member; filling a powder sample containing a material to be analyzed into the sample holding section; compressing the powder sample by pressurizing the filled powder sample from the other end to the one end of the sample holding section; and removing the covering member from the sample holding section, thereby producing the sample containing object which includes the sample holding section and the compressed powder sample and from which the compressed powder sample is exposed from the one end.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 8, 2020
    Assignee: HORIBA, LTD.
    Inventors: Akira Fujimoto, Tatsuhito Nakamura, Hiroko Yamada
  • Publication number: 20200039813
    Abstract: According to one embodiment, a MEMS device is disclosed. The MEMS device includes a substrate, and a MEMS vibrator provided on the substrate. The MEMS vibrator includes a first vibration portion disposed above the substrate, and a control electrode to control a vibration property of the first vibration portion. The control electrode is disposed without contacting the first vibration portion.
    Type: Application
    Filed: March 13, 2019
    Publication date: February 6, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Fujimoto, Yoshihiko Kurui, Hideyuki Tomizawa, Tomohiro Saito, Akihiro Kojima
  • Publication number: 20190084825
    Abstract: According to one embodiment, a connection structure is disclosed. The connection structure includes a plug having conductivity, a first insulating film, and an electrode. The first insulating film covers a side surface of the plug. The electrode is provided on an upper surface of the plug, and includes a polycrystalline silicon germanium layer and an amorphous silicon germanium layer. The polycrystalline silicon germanium layer is in contact with at least part of the upper surface of the plug without an intervention the amorphous silicon germanium layer.
    Type: Application
    Filed: February 28, 2018
    Publication date: March 21, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki TOMIZAWA, Tomohiro Saito, Akira Fujimoto, Yoshikiko Kurui, Akihiro Kojima
  • Publication number: 20190040415
    Abstract: An object of the present invention is to solve problems in terms of stagnation of research on norovirus by providing a cultured transgenic cell or a transgenic animal in which murine norovirus (MNV) can be grown across the barrier of host specificity in mammalian cells, and providing a screening method that uses the cultured transgenic cell or the transgenic animal. The present inventors have found that MNV infection is determined in a cultured transgenic mammalian cell or a mammal possessing the cultured transgenic mammalian cell as its own cell, the cultured transgenic mammalian cell containing one or more species selected from the entirety or a portion of the murine CD300F gene and/or a CD300 family gene having an extracellular domain nucleotide sequence similar to that of the murine CD300F gene. The present inventors have solved the aforementioned problems by providing, for example, a norovirus-related drug screening method on the basis of this finding.
    Type: Application
    Filed: February 1, 2017
    Publication date: February 7, 2019
    Applicants: JAPAN AS REPRESENTED BY DIRECTOR-GENERAL OF NATIONAL INSTITUTE OF INFECTIOUS DISEASES, DENKA COMPANY LIMITED, NATIONAL CENTER FOR GERIATRICS AND GERONTOLOGY
    Inventors: Kei HAGA, Akira FUJIMOTO, Reiko TODAKA, Kazuhiko KATAYAMA, Akira NAKANISHI, Motohiro MIKI, Sakari SEKINE, Hiroshi OTSUKA, Shigetaka MIMORI
  • Publication number: 20180266960
    Abstract: A method, to perform glow discharge optical emission spectrometry using a glow discharge tube equipped with an electrode having an end section, for producing a sample containing object that is to be disposed so as to be opposed to the end section, comprises: covering one end of a sample holding section having a cylindrical shape and being open at both ends using a covering member; filling a powder sample containing a material to be analyzed into the sample holding section; compressing the powder sample by pressurizing the filled powder sample from the other end to the one end of the sample holding section; and removing the covering member from the sample holding section, thereby producing the sample containing object which includes the sample holding section and the compressed powder sample and from which the compressed powder sample is exposed from the one end.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Inventors: Akira FUJIMOTO, Tatsuhito Nakamura, Hiroko Yamada
  • Patent number: 9914637
    Abstract: According to one embodiment, an electronic device includes a base region, an element portion located on the base region, the element portion including a movable portion, and a protective film overlying the element portion and forming a cavity on an inner side of the protective film. The protective film includes a first protective layer and a second protective layer located on the first protective layer. A hole extends in a direction parallel to a main surface of the base region, and the second protective layer covers the hole.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Naofumi Nakamura, Tamio Ikehashi
  • Patent number: 9905258
    Abstract: According to one embodiment, a magnetic recording medium with high magnetic recording characteristics and improved corrosion resistance is obtained. The magnetic recording medium includes a substrate, an orientation control layer provided on the substrate and made from a Ni alloy or an Ag alloy, a nonmagnetic seed layer provided to be in contact with the orientation control layer, a perpendicular magnetic recording layer containing Fe or Co and Pt as main components. The nonmagnetic seed layer is formed of Ag particles, Ge grain boundaries and a compound X, and the compound X is selected from an oxide, nitride or carbide of aluminum, titanium, chromium, silicon and tantalum and also distributed in both the Ag particles and Ge grain boundaries.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Iwasaki, Akira Fujimoto
  • Patent number: 9793055
    Abstract: According to one embodiment, an electronic device includes an underlying region, a variable capacitor including fixed electrodes and movable electrodes alternately arranged in a direction not perpendicular to a main surface of the underlying region, and a protective film which covers the variable capacitor and includes a conductive portion electrically connected to the fixed electrodes and having a hole.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 17, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Fujimoto, Naofumi Nakamura, Tamio Ikehashi
  • Patent number: 9776854
    Abstract: According to one embodiment, a method of manufacturing a device is provided. A amorphous metal layer is formed. A metal layer containing metal and having a crystal plane oriented to a predetermined plane is formed on the amorphous metal layer. A first layer containing semiconductor including silicon, and metal identical to the metal contained in the metal layer is formed on the metal layer. The first layer is changed to a second layer containing a compound of the semiconductor and the metal, the compound having a crystal plane oriented to the predetermined plane. A third layer containing polycrystalline silicon-germanium and having a crystal plane oriented to the predetermined plane is formed on the second layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 3, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Fujimoto, Naofumi Nakamura, Tamio Ikehashi
  • Publication number: 20170267517
    Abstract: According to one embodiment, an electronic device includes a base region, an element portion located on the base region, the element portion including a movable portion, and a protective film overlying the element portion and forming a cavity on an inner side of the protective film. The protective film includes a first protective layer and a second protective layer located on the first protective layer. A hole extends in a direction parallel to a main surface of the base region, and the second protective layer covers the hole.
    Type: Application
    Filed: August 29, 2016
    Publication date: September 21, 2017
    Inventors: Akira FUJIMOTO, Naofumi NAKAMURA, Tamio IKEHASHI
  • Publication number: 20170117010
    Abstract: According to one embodiment, a magnetic recording medium with high magnetic recording characteristics and improved corrosion resistance is obtained. The magnetic recording medium includes a substrate, an orientation control layer provided on the substrate and made from a Ni alloy or an Ag alloy, a nonmagnetic seed layer provided to be in contact with the orientation control layer, a perpendicular magnetic recording layer containing Fe or Co and Pt as main components. The nonmagnetic seed layer is formed of Ag particles, Ge grain boundaries and a compound X, and the compound X is selected from an oxide, nitride or carbide of aluminum, titanium, chromium, silicon and tantalum and also distributed in both the Ag particles and Ge grain boundaries.
    Type: Application
    Filed: January 27, 2016
    Publication date: April 27, 2017
    Inventors: Takeshi Iwasaki, Akira Fujimoto
  • Patent number: 9595285
    Abstract: According to one embodiment, a magnetic recording medium includes an orientation control layer formed on a non-magnetic substrate, the orientation control layer made of a Ni alloy or Ag alloy having fcc structure, a non-magnetic seed layer made of Ag, Ge, and a metal X selected from the group consisting of Al, Mg, Au, and Ti, a non-magnetic intermediate layer made of Ru or Ru alloy, and a magnetic recording layer. The orientation control layer is in contact with the non-magnetic seed layer.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Iwasaki, Akira Fujimoto
  • Publication number: 20160289060
    Abstract: According to one embodiment, a method of manufacturing a device is provided. A amorphous metal layer is formed. A metal layer containing metal and having a crystal plane oriented to a predetermined plane is formed on the amorphous metal layer. A first layer containing semiconductor including silicon, and metal identical to the metal contained in the metal layer is formed on the metal layer. The first layer is changed to a second layer containing a compound of the semiconductor and the metal, the compound having a crystal plane oriented to the predetermined plane. A third layer containing polycrystalline silicon-germanium and having a crystal plane oriented to the predetermined plane is formed on the second layer.
    Type: Application
    Filed: March 11, 2016
    Publication date: October 6, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira FUJIMOTO, Naofumi NAKAMURA, Tamio IKEHASHI
  • Publication number: 20160293336
    Abstract: According to one embodiment, an electronic device includes an underlying region, a variable capacitor including fixed electrodes and movable electrodes alternately arranged in a direction not perpendicular to a main surface of the underlying region, and a protective film which covers the variable capacitor and includes a conductive portion electrically connected to the fixed electrodes and having a hole.
    Type: Application
    Filed: September 9, 2015
    Publication date: October 6, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira FUJIMOTO, Naofumi NAKAMURA, Tamio IKEHASHI
  • Patent number: 9444012
    Abstract: A semiconductor light emitting device includes a structural body, a first electrode layer, and a second electrode layer. The structural body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer between the first and second semiconductor layers. The first electrode layer includes a metal portion, plural first opening portions, and at least one second opening portion. The metal portion has a thickness of not less than 10 nanometers and not more than 200 nanometers along a direction from the first semiconductor layer toward the second semiconductor layer. The plural first opening portions each have a circle equivalent diameter of not less than 10 nanometers and not more than 1 micrometer. The at least one second opening portion has a circle equivalent diameter of more than 1 micrometer and not more than 30 micrometers.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Akira Fujimoto, Ryota Kitagawa, Takanobu Kamakura, Shinji Nunotani, Eishi Tsutsumi, Masaaki Ogawa
  • Patent number: 9437779
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Asakawa, Akira Fujimoto, Ryota Kitagawa, Kumi Masunaga, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 9412405
    Abstract: According to one embodiment, disclosed is a pattern forming method including preparing a second dispersion by adding a second protective group and second solvent to fine particles including a first protective group whose surface polarity is close to that of the substrate, the fine particles containing, at least on the surface thereof, a material selected from Al, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, Au, Ag, Pd, Cu, Pt, and an oxide thereof, modifying the fine particles including the first protective group with the second protective group, adding a viscosity adjustment agent to the dispersion containing the fine particles to prepare a coating solution, and applying the coating solution on the substrate to form a fine particle layer thereon.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori Kimura, Akira Fujimoto, Akira Watanabe
  • Patent number: 9331248
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 3, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumi Masunaga, Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 9324914
    Abstract: A semiconductor light-emitting device capable of keeping high luminance intensity even if electric power increases, and suitable for lighting instruments such as lights and lamps. The semiconductor device includes a metal electrode layer provided with openings, and is so large in size that the electrode layer has, for example, an area of 1 mm2 or more. The openings have a mean diameter of 10 nm to 2 ?m, and penetrate through the metal electrode layer. The metal electrode layer can be produced by use of self-assembling of block copolymer or by nano-imprinting techniques.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: April 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Fujimoto, Ryota Kitagawa, Koji Asakawa
  • Patent number: 9318661
    Abstract: A semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a first electrode layer, a light emitting layer, a second semiconductor layer, a third semiconductor layer and a second electrode layer. The first electrode layer includes a metal portion having a plurality of opening portions. The opening portions penetrate the metal portion and have an equivalent circle diameter of a shape of the opening portions. The light emitting layer is between the first semiconductor layer and the first electrode layer. The second semiconductor layer of a second conductivity type is between the light emitting layer and the first electrode layer. The third semiconductor layer of a second conductivity type is between the second semiconductor layer and the first electrode layer. The second electrode layer is connected to the first semiconductor layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumi Masunaga, Ryota Kitagawa, Eishi Tsutsumi, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani